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dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 dm3730, dm3725 digital media processors check for samples: dm3730 , dm3725 1 dm3730, dm3725 digital media processors 1.1 features 123456 ? load-store architecture with ? dm3730/25 digital media processors: non-aligned support C compatible with omap ? 3 architecture ? 64 32-bit general-purpose registers C arm ? microprocessor (mpu) subsystem ? instruction packing reduces code size ? up to 1-ghz arm ? cortex ? -a8 core ? all instructions conditional also supports 300, 600, and 800-mhz operation ? additional c64x+ tm enhancements ? neon ? simd coprocessor C protected mode operation C high performance image, video, audio C expectations support for error (iva2.2 tm ) accelerator subsystem detection and program redirection ? up to 800-mhz tms320c64x+ tm dsp core C hardware support for modulo loop also supports 260, 520, and 660-mhz operation operation C c64x+ tm l1/l2 memory architecture ? enhanced direct memory access (edma) ? 32k-byte l1p program ram/cache controller (128 independent channels) (direct mapped) ? video hardware accelerators ? 80k-byte l1d data ram/cache (2-way C powervr sgx ? graphics accelerator set- associative) (dm3730 only) ? 64k-byte l2 unified mapped ram/cache ? tile based architecture delivering up to (4- way set-associative) 20 mpoly/sec ? 32k-byte l2 shared sram and 16k-byte ? universal scalable shader engine: l2 rom multi-threaded engine incorporating pixel C c64x+ tm instruction set features and vertex shader functionality ? byte-addressable (8-/16-/32-/64-bit data) ? industry standard api support: ? 8-bit overflow protection opengles 1.1 and 2.0, openvg1.0 ? bit-field extract, set, clear ? fine grained task switching, load ? normalization, saturation, bit-counting balancing, and power management ? compact 16-bit instructions ? programmable high quality image ? additional instructions to support anti-aliasing complex multiplies C advanced very-long-instruction-word C external memory interfaces: (vliw) tms320c64x+ tm dsp core ? sdram controller (sdrc) ? eight highly independent functional C 16, 32-bit memory controller with units 1g-byte total address space ? six alus (32-/40-bit); each supports C interfaces to low-power sdram single 32- bit, dual 16-bit, or quad 8-bit, C sdram memory scheduler (sms) and arithmetic per clock cycle rotation engine ? two multipliers support four 16 x 16-bit ? general purpose memory controller multiplies (32-bit results) per clock (gpmc) cycle or eight 8 x 8-bit multiplies (16-bit results) per clock cycle C 16-bit wide multiplexed address/data 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 powervr sgx is a trademark of imagination technologies ltd. 3 omap is a trademark of texas instruments. 4 cortex, neon are trademarks of arm limited. 5 arm is a registered trademark of arm ltd. 6 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2010 C 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com bus ? glueless interface to common video decoders C up to 8 chip select pins with 128m-byte address space per chip ? resize engine select pin C resize images from 1/4x to 4x C glueless interface to nor flash, C separate horizontal/vertical control nand flash (with ecc hamming C system direct memory access (sdma) code calculation), sram and controller (32 logical channels with pseudo-sram configurable priority) C flexible asynchronous protocol C comprehensive power, reset, and clock control for interface to custom logic management (fpga, cpld, asics, etc.) ? smartreflex tm technology C nonmultiplexed address/data mode ? dynamic voltage and frequency scaling (limited 2k-byte address space) (dvfs) C 1.8-v i/o and 3.0-v (mmc1 only), C arm ? cortex ? -a8 core 0.9-v to 1.2-v adaptive processor core ? armv7 architecture voltage C trustzone ? 0.9-v to 1.1-v adaptive core logic voltage C thumb ? -2 note: these are default operating performance point (opp) voltages and could C mmu enhancements be optimized to lower values using ? in-order, dual-issue, superscalar smartreflex avs. microprocessor core C commercial, industrial, and extended ? neon multimedia architecture temperature grades ? over 2x performance of armv6 simd C serial communication ? supports both integer and floating point ? 5 multichannel buffered serial ports simd (mcbsps) ? jazelle ? rct execution environment C 512 byte transmit/receive buffer architecture (mcbsp1/3/4/5) ? dynamic branch prediction with branch C 5k-byte transmit/receive buffer target address cache, global history (mcbsp2) buffer, and 8-entry return stack C sidetone core support (mcbsp2 and ? embedded trace macrocell (etm) 3 only) for filter, gain, and mix support for non-invasive debug operations C arm cortex-a8 memory architecture: C direct interface to i2s and pcm device ? 32k-byte instruction cache (4-way and t buses set-associative) C 128 channel transmit/receive mode ? 32k-byte data cache (4-way ? four master/slave multichannel serial set-associative) port interface (mcspi) ports ? 256k-byte l2 cache ? high-speed/full-speed/low-speed usb C 32k-byte rom otg subsystem (12-/8-pin ulpi interface) C 64k-byte shared sram ? high-speed/full-speed/low-speed C endianess: multiport usb host subsystem ? arm instructions - little endian C 12-/8-pin ulpi interface or 6-/4-/3-pin ? arm data C configurable serial interface ? dsp instructions/data - little endian ? one hdq/1-wire interface ? removable media interfaces: ? four uarts (one with infrared data C three multimedia card (mmc)/ secure digital association [irda] and consumer infrared (sd) with secure data i/o (sdio) [cir] modes) ? test interfaces ? three master/slave high-speed inter-integrated circuit (i2c) controllers C ieee-1149.1 (jtag) boundary-scan compatible C camera image signal processing (isp) C embedded trace macro interface (etm) ? ccd and cmos imager interface C serial data transport interface (sdti) ? memory data input ? 12 32-bit general purpose timers ? bt.601/bt.656 digital ycbcr 4:2:2 (8-/10-bit) interface ? 2 32-bit watchdog timers 2 dm3730, dm3725 digital media processors copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 ? 1 32-bit secure watchdog timer ? packages: ? 1 32-bit 32-khz sync timer C 515-pin s-pbga package (cbp suffix), .5mm ball pitch (top), .4mm ball pitch (bottom) ? up to 188 general-purpose i/o (gpio) pins (multiplexed with other device functions) C 515-pin s-pbga package (cbc suffix), .65mm ball pitch (top), .5mm ball ? 45-nm cmos technology pitch (bottom) ? package-on-package (pop) implementation for C 423-pin s-pbga package (cus memory stacking (not available in cus suffix), .65mm ball pitch package) copyright ? 2010 C 2011, texas instruments incorporated dm3730, dm3725 digital media processors 3 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 1.2 description the dm37x generation of high-performance, digital media processors are based on the enhanced device architecture and are integrated on ti's advanced 45-nm process technology. this architecture is designed to provide best in class arm and graphics performance while delivering low power consumption. this balance of performance and power allow the device to support the following example applications: ? portable data terminals ? navigation ? auto infotainment ? gaming ? medical imaging ? home automation ? human interface ? industrial control ? test and measurement ? single board computers the device can support numerous hlos and rtos solutions including linux and windows embedded ce which are available directly from ti. additionally, the device is fully backward compatible with previous cortex ? -a8 processors and omap ? processors. this dm3730/25 digital media processor data manual presents the electrical and mechanical specifications for the dm3730/25 digital media processor. the information contained in this data manual applies to the commercial, industrial, and extended temperature versions of the dm3730/25 digital media processor unless otherwise indicated. it consists of the following sections: ? a description of the dm3730/25 terminals: assignment, electrical characteristics, multiplexing, and functional description ? a presentation of the electrical characteristics requirements: power domains, operating conditions, power consumption, and dc characteristics ? the clock specifications: input and output clocks, dpll and dll ? a description of thermal characteristics, device nomenclature, and mechanical data about the available packaging 4 dm3730, dm3725 digital media processors copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 1.3 functional block diagram the functional block diagram of the dm3730/25 digital media processor is shown below. figure 1-1. dm3730/25 functional block diagram copyright ? 2010 C 2011, texas instruments incorporated dm3730, dm3725 digital media processors 5 submit documentation feedback product folder link(s): dm3730 dm3725 64 64 async 64 64 l2$ 256k mpu subsystem powervr sgx graphics accelerator tm 32 32 32 channel system dma 32 32 parallel tv amp lcd panel cvbs or s-video dual output 3-layer display processor (1xgraphics, 2xvideo) temporal dithering sdtv qcif support ? 32 camera isp image capture hardware image pipeline camera (parallel) 64 hs usb host hs usb otg 32 l3 interconnect network-hierarchial, performance, and power driven 64kb on-chip ram 32 32kb on-chip rom 32 sms: sdram memory scheduler/ rotation 64 sdrc: sdram memory controller l4 interconnect 32 system controls prcm 2xsmartreflex tm control module external peripherals interfaces peripherals: 4xuart, 3xhigh-speed i2c, 5xmcbsp (2x with sidetone/audio buffer) 4xmcspi, 6xgpio 3xhigh-speed mmc/sdio hdq/1 wire, 6xmailboxes 12xgptimers, 2xwdt, 32k sync timer gpmc: general purpose memory controller nand/ nor flash, sram 32 emulation debug: sdti, etm, jtag external and stacked memories 32 iva 2.2 subsystem tms320dm64x+ dsp imaging video and audio processor 32k/32k l1$ 48k l1d ram 64k l2$ 32k l2 ram 16k l2 rom video hardware 64 32 async 64 32 arm cortex?- a8 ? core trustzone 32k/32k l1$
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com revision history note: page numbers for previous revisions may differ from page numbers in the current version. this data sheet revision history highlights the technical changes made from the previous to the current revision. revision history section additions/changes/deletions changed: ? table 2-1. ball characteristics (cbp pkg.). removed restriction note from gpio_16. terminal description ? table 2-2. ball characteristics (cbc pkg.). removed restriction note from gpio_16. ? table 2-3. ball characteristics (cus pkg.). removed restriction note from gpio_16. changed: ? table 3-1. absolute maximum rating over junction temperature range. added jtag to electrical characteristics vesd. ? table 3-5. dc electrical characteristics. removed usim ball r27. added note on rise and fall times for these tables: ? input clock requirements ? sys_xtalin squarer input clock timing requirements - bypass mode ? sys_32k input clock timing requirements ? sys_altclk input clock timing requirements clock specifications ? sys_clkout1 output clock switching characteristics ? sys_clkout2 output clock switching characteristics added: ? table 4-2, crystal electrical characteristics. added entry for dl - crystal drive level 6 dm3730, dm3725 digital media processors copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 2 terminal description 2.1 terminal assignment figure 2-1 through figure 2-5 show the ball locations for the 515- and 423- ball plastic ball grid array (s-pbga) packages. table 2-1 through table 2-25 indicate the signal names and ball grid numbers for both packages. note : there are no balls present on the top of the 423-ball s-pbga package. figure 2-1. dm3730/25 digital media processor cbp s-pbga-n515 package (bottom view) copyright ? 2010 C 2011, texas instruments incorporated terminal description 7 submit documentation feedback product folder link(s): dm3730 dm3725 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a b c d e f g h j k l m n p t r u v w y aa ab ac 24 25 26 27 28 ad ae af ag ah 1 030-001
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 2-2. dm3730/25 digital media processor cbp s-pbga-n515 package (top view) 8 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 a c d e g k l m n p t r u v w y ab b f h j aa ac 22 21 20 18 17 16 15 13 12 10 9 8 7 6 5 4 3 2 1 11 14 19 23 030-002
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 2-3. dm3730/25 digital media processor cbc s-pbga-515 package (bottom view) copyright ? 2010 C 2011, texas instruments incorporated terminal description 9 submit documentation feedback product folder link(s): dm3730 dm3725 af ae adac ab aa y w v u t r p n m l k j h g f e dc b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 2-4. dm3730/25 digital media processor cbc s-pbga-515 package (top view) 10 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 aa y w v u t r p n m l k j h g f e dc b a 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 2-5. dm3730/25 digital media processor cus s-pbga-n423 package (bottom view) 2.2 pin assignments 2.2.1 pin map (top view) the following pin maps show the top views of the 515-pin spbga package [cbp] , the 515-pin spbga package [cbc] , and the 423-pin spbga package [cus] pin assignments in four quadrants (a, b, c, and d). note : a pin with an "nc" designator indicates no connection. for proper device operation, these pins must be left unconnected. copyright ? 2010 C 2011, texas instruments incorporated terminal description 11 submit documentation feedback product folder link(s): dm3730 dm3725 ad ac ab aa y w v u t r p n m l k j h g f e d cb a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com a. top views are provided to assist in hardware debugging efforts. figure 2-6. cbp pin map [quadrant a - top view] 12 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 a 9 8 vdds_mem 7 6 5 4 3 2 nc 1 b vdds_mem vss c d e f g h j k vdds_mem nc vdds_mem nc vss vss vdd_core vdd_core vss vss gpmc_nwe gpmc_nadv _ale vdds_mem vdds_mem nc gpmc_nbe0 _cle gpmc_noe nc gpmc_wait3 vdd_core gpmc_ncs1 gpmc_d8 gpmc_nwp vss vdd_core vss vdds_mem vdds_mem vdd_mpu _iva gpmc_wait1 gpmc_a10 gpmc_d9 gpmc_d0 gpmc_a4 gpmc_wait2 vdd_mpu _iva gpmc_ncs0 vss l m n p vdd_mpu _iva gpmc_wait0 gpmc_a9 gpmc_d2 gpmc_d1 gpmc_ncs7 gpmc_a2 gpmc_a8 pop_k2 _m2 vss gpmc_a1 gpmc_a7 pop_l2 _n2 pop_u1 _n1 vss gpmc_d3 gpmc_d10 vss gpmc_ncs6 vss gpmc_a3 14 nc 13 nc 12 11 10 nc vdds_mem nc vdds_mem vss vss vss vss nc nc nc nc vss vss vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vss vdd_mpu _iva vdd_mpu _iva vss vdd_mpu _iva nc vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vss pop_y23 _m1 nc nc ncnc ncnc nc ncnc nc nc nc nc nc nc nc nc ncnc nc nc nc nc nc nc ncnc nc nc nc nc nc nc nc nc
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 2-7. cbp pin map [quadrant b - top view] copyright ? 2010 C 2011, texas instruments incorporated terminal description 13 submit documentation feedback product folder link(s): dm3730 dm3725 a 20 21 22 23 24 25 cam_d5 26 27 pop_a22 _a27 28 b cam_d2 cam_d10 vss c d dss_hsync e f g h j k vdds_mem cam_vs cam_hs pop_a23 _a28 vdds_mem cam_wen cam_xclkb pop_b23 _b28 vss cam_fld cam_d3 vss cam_xclka cam_d11 cam_pclk vdds_mem vss vdd_core cam_d4 dss_vsync dss_pclk vdd_core dss_data6 dss_acbias dss_data20 vdds dss_data8 dss_data7 uart3_rx _irrx dss_data9 vss vdds_mem dss_data19 dss_data18 dss_data17 vdds vdd_core hdq_sio dss_data21 pop_k1 _j28 vss mcbsp1_fsx cam_d8 cam_d6 vdds_ mmc1 vdd_core dss_data16 cam_strobe vdd_core l m n p vss vss cam_d9 cam_d7 vdd_core mmc1 _cmd vss vdd_core mmc1 _dat2 mmc1 _dat1 mmc1 _dat0 mmc1 _clk gpio_127 gpio_126 mmc1 _dat3 vdds_x vdd_core vdd_core 15 pop_a12_a15 16 nc 17 18 19 nc nc vdds_mem nc nc vdds_mem vdds_mem nc vss vdd_core vdds_mem nc vss nc nc uart3_cts _rctx uart3_rts _sd vss vss vdd_core vdda_dplls _dll vdd_core vss vss vss vss vdd_mpu _iva nc nc vdd_core vdd_core vdd_core vss i2c1_sda cap_vdd _sram_core i2c1_scl mcbsp2_dx mcbsp2 _clkx mcbsp2_fsx uart3_tx _irtx nc ncnc ncnc nc nc ncnc nc pop_b12 _b15 vdds pop_h22 _j27 pop_k22 _m26
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 2-8. cbp pin map [quadrant c - top view] 14 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 ah 9 etk_d5 8 etk_d15 7 6 5 4 mmc2 _dat1 3 2 pop_ac2 _ah2 1 ag mmc2 _cmd mmc2 _dat2 vss af etk_d8 ae mmc2 _dat7 ad ac ab aa y w etk_d13 vdds_mem mmc2 _dat0 etk_d9 etk_d14 etk_d12 vss vss pop_ab1 _ag1 etk_d11 mcbsp3_dx mcbsp3 _clkx mmc2 _dat5 mmc2 _dat3 mmc2 _dat6 vdd_core mcbsp3_dr mcbsp3_fsx mmc2 _clk mcbsp4 _clkx mcbsp4_dx mcbsp4_dr vdd_core mcspi1_cs1 mcspi1 _cs0 mcbsp4 _fsx mcspi1_clk mcspi1 _cs3 mcspi1 _cs2 uart1_tx mcspi1 _somi mcspi2_clk pop_aa1 _aa1 vdd_mpu _iva mcspi2 _cs0 mcspi2 _somi mcspi2_ simo gpmc_d15 vdd_mpu _iva uart1_cts vss gpmc_d7 gpmc_d14 vdds uart1_rx uart1_rts mcspi1 _simo mmc2 _dat4 etk_d10 v u t r vss gpmc_ncs2 mcspi2 _cs1 gpmc_d6 gpmc_d5 gpmc_ncs3 cap_vdd _bb_mpu _iva gpmc_nbe1 vss vdds_mem vdd_mpu _iva gpmc_clk gpmc_a5 gpmc_d13 gpmc_d4 vdd_mpu _iva gpmc_ncs5 gpmc_a6 gpmc_d12 gpmc_d11 vdds_mem gpmc_ncs4 vss cap_vdd _sram _mpu_iva 14 etk_d7 13 12 11 10 i2c3_scl etk_d2 pop_ac9 _ah11 i2c3_sda pop_ab11 _ag13 etk_d1 pop_ab9 _ag11 etk_d6 vss etk_d0 etk_clk sys_boot2 etk_d3 etk_d4 etk_ctl jtag_tck jtag_rtck jtag_emu1 vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vss vss vss vdda_wkup _bg_bb vss jtag_emu0 vss vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vss vdd_mpu _iva vss vdd_mpu _iva pop_aa2 _aa2 vdds vdds vddsvdds pop_u2 _af2 pop_ac8 _af1 pop_ab8 _ag10 pop_ac11 _ah13 pop_ac13 _ah10 pop_ac1 _ah1
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 2-9. cbp pin map [quadrant d - top view] copyright ? 2010 C 2011, texas instruments incorporated terminal description 15 submit documentation feedback product folder link(s): dm3730 dm3725 ah 20 cap_vddu _array 21 vss 22 23 24 25 sys _nrespwron 26 27 pop_ac22 _ah27 28 ag dss_data4 sys_clkout1 vdds af vss ae i2c4_sda ad ac ab aa y w dss_data1 dss_data3 dss_data5 vdds dss_data0 dss_data2 sys_boot1 pop_ab23 _ag28 sys_boot6 sys_off _mode sys _nreswarm sys_boot0 sys_clkreq sys_nirq vss sys_boot5 vdds vdd_core uart2_rx i2c4_scl dss_data11 dss_data10 vss vss dss_ data22 dss_ data23 uart2_cts dss_data13 dss_data12 uart2_tx dss_ data15 dss_ data14 vss vssa_dac cvideo1 _out cvideo1 _rset cvideo2 _vfb cvideo2 _out vss uart2_rts sys_32k sys_clkout2 v u t r hsusb0 _data7 hsusb0 _data6 hsusb0 _data5 hsusb0 _data4 hsusb0 _data3 hsusb0 _data2 hsusb0 _data1 hsusb0_stp hsusb0_nxt hsusb0 _data0 hsusb0_clk vss gpio_128 hsusb0_dir gpio_129 vdda_dac 15 16 pop_ac14 _ah16 17 18 19 i2c2_scl cam_d1 gpio_115 pop_ab13 _ag15 cam_d0 vdds sys_xtalout sys_boot3 sys_boot4 i2c2_sda vdd_core vdd_core sys_xtalin jtag_tdi mcbsp1 _clkr vdd_core vdd_core mcbsp1_dx mcbsp1 _clkx vdd_core vdd_core mcbsp1_dr mcbsp_clks vss mcbsp2_dr vss cap_vddu _wkup _logic vdda_dpll _per jtag_tms _tmsc jtag_tdo vdd_core sys_ xtalgnd vdd_core vdd_mpu _iva vdd_core vss vss vdds_sram vss vdd_mpu _iva jtag_ntrst vdd_core vdd_core vdd_core vss mcbsp1_fsr nc nc cvideo1 _vfb pop_aa23 _ae28 vdds pop_h23 _af28 pop_aa22 _af27 vdds pop_l1 _ah15 gpio_113 pop_ac23 _ah28 vss gpio_114 gpio_112 vdds
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com a. top views are provided to assist in hardware debugging efforts. figure 2-10. cbc pin map [quadrant a - top view] 16 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 a 9 8 7 6 5 4 3 2 nc 1 b vss c d e f g h j k gpmc _a11 pop_a1 _a1 nc gpmc_ ncs2 vdds uart1 _rx vdd_mpu _iva mmc2 _dat7 vss l m n gpmc _d14 pop_j1 _l1 mcbsp3 _dr cap_vdd _sram _mpu_iva vdds 13 12 11 10 vdd_mpu _iva vss vdd_mpu _iva vdda_ dplls_ dll vdd_mpu _iva gpmc_ ncs4 gpmc_ wait2 nc vss cap_ vdd_bb _mpu_iva nc sys_ boot6 i2c2_scl vssvss nc vss nc nc nc nc vss nc vdd_ core gpmc_ ncs6 gpmc_ ncs3 ncnc ncnc nc ncnc ncnc nc vdds nc nc nc nc gpmc_ wait3 gpmc_ ncs7 gpmc_ ncs5 sys_ boot2 sys_ boot1 i2c2_sda gpmc _a9 gpmc _a10 gpmc _a7 gpmc _a8 sys_ boot3 sys_ boot4 gpmc _a5 gpmc _a6 sys_ boot0 nc vss gpmc _a4 sys_ boot5 vdds gpmc _a2 gpmc _a3 vss gpmc _nbe1 gpmc _a1 nc nc vss gpmc _nbe0 _cle nc mmc2 _dat6 gpmc _nwe gpmc _d15 mmc2 _dat5 uart1 _tx gpmc _clk gpmc _noe vss nc vdd_mpu _iva vss vdd_mpu _iva nc vss vdd_mpu _iva nc nc nc nc nc nc nc nc nc vss nc vdd_ core vdds nc nc nc ncnc nc nc vdd_mpu _iva vdd_mpu _iva ncnc vss vdd_mpu _iva
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 2-11. cbc pin map [quadrant b - top view] copyright ? 2010 C 2011, texas instruments incorporated terminal description 17 submit documentation feedback product folder link(s): dm3730 dm3725 a 18 19 20 21 22 23 cam_wen 24 25 26 b nc cam_d2 c d e f g h j k pop_b16 _a20 nc nc nc nc pop_ b21_b26 nc nc nc cam_ xclka nc nc nc nc uart3_rts_sd dss_ data20 dss_ acbias dss_ data7 hdq_sio vdd_ core l m n vdds_ mmc1 cam_d9 14 nc 15 16 17 nc nc nc nc nc nc nc nc vss nc vss cap_vddu_ wkup_ logic vss vdd_ core i2c1_scl nc nc nc vdds ncnc nc nc nc vss vss nc nc nc vss cam_d3 cam_d5 cam_d4 vdds cam_fld cam_hs cam_vs vss pop_ a20_a25 pop_ a21_a26 cam_ pclk cam_d10 cam_ strobe cam_d11 dss_ pclk cam_ xclkb dss_ data6 uart3_ cts_ rctx uart3_ tx_ irtx vss nc uart3_ rx_ irrx dss_ data8 dss_ data9 i2c1_sda pop_ h21_k26 vss dss_ hsync nc vss vdds dss_ data16 dss_ data17 dss_ data19 dss_ vsync dss_ data18 nc cam_d8 dss_ data21 nc nc gpio_126 vdd_ core nc vss vdd_ core nc nc nc nc nc nc nc nc vdds nc nc vdds nc nc nc mmc1_ dat2 nc cap_vdd _sram_ core vdds vss mmc1_ cmd mmc1_ dat0 mmc1_ dat1 mmc1_ dat3 mmc1_ clk nc vss
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 2-12. cbc pin map [quadrant c - top view] 18 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 af 9 etk_d14 8 7 6 5 4 3 2 1 ae ad ac ab aa y w v u etk_d13 sys_ nres warm pop_t2 _y2 nc etk_d9 gpmc _d8 vdd_mpu _iva t r p pop_n2 _t2 gpmc _d10 mcbsp4 _dx uart1 _rts mcspi1 _clk nc mcbsp3 _dx gpmc _d13 mcspi1 _simo 13 12 11 10 gpmc_ nadv_ale jtag_ rtck nc vdd_mpu _iva sys_ nresp wron sys_off _mode vdd_mpu _iva vdd_mpu _iva vdds_ sram vss i2c3_scl pop_aa11 _af13 pop_y9_ _af10 nc uart1 _cts vdd_ core mcspi1 _cs0 mcspi1 _somi jtag_ tdo vdd_ core vss nc vss vss mcspi1 _cs1 mcspi1 _cs2 mmc2 _cmd mmc2 _dat0 mmc2 _dat1 mcspi1 _cs3 vdds mcbsp4 _fsx gpmc _d12 gpmc _d11 mcbsp3 _clkx mcbsp4 _dr vdd_ core mcspi2 _somi mmc2 _dat3 mmc2 _dat2 vdd_mpu _iva mmc2 _dat4 mcspi2 _cs1 mcspi2 _cs0 vdd_mpu _iva mcbsp4 _clkx mcbsp3 _fsx vss mcspi2 _clk mcspi2 _simo vdd_mpu _iva mmc2 _clk sys_ clkout2 vdd_mpu _iva vdd_mpu _iva vdd_ core vss vdds etk_d4 gpmc _d9 gpmc _d1 gpmc _d0 etk_d3 etk_d8 etk_d5 etk_clk etk_ctl vss gpmc _d3 gpmc _d2 etk_d0 i2c3_sda gpmc _d7 gpmc _nwp vdds gpmc _wait1 nc vss gpmc _wait0 nc nc nc nc nc nc gpmc _ncs0 gpmc _d5 etk_d1 etk_d2 etk_d7 gpmc _ncs1 gpmc _d6 nc pop_w2 _ae2 etk_d6 etk_d10 gpmc _d4 etk_d12 vss nc etk_d15 vdds nc nc nc pop_aa10 _af12 nc pop_y7_ _af8 etk_d11 pop_aa6 _af5 pop_y2 _af4 nc nc
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 2-13. cbc pin map [quadrant d - top view] copyright ? 2010 C 2011, texas instruments incorporated terminal description 19 submit documentation feedback product folder link(s): dm3730 dm3725 af 18 19 sys_ xtalin 20 21 22 23 sys _xtalgnd 24 25 26 ae dss_ data1 ad ac ab aa y w v u pop_y21 _ae26 vdd_ core uart2 _cts dss_ data13 dss_ data12 cvideo1 _rset vssa_ dac cvideo2 _out cvideo2 _vfb pop_ p21_u26 t r p vdds vdds_x nc cam_d7 14 pop_aa12 _af14 15 16 17 cam_d1 cam_d0 gpio_113 mcbsp1 _clkr hsusb0 _data2 mcbsp2 _dx gpio_129 gpio_128 vdda_wkup_ bg_bb i2c4_sda jtag_tms _tmsc jtag_tdi vss vdda_ dpll_per jtag_ ntrst sys_nirq gpio_127 vss pop_aa21 _af26 sys_ clkout1 cap _vddu _array mcbsp1 _dr hsusb0 _stp mcbsp2 _clkx mcbsp1 _fsx jtag_ emu1 cam_d6 nc nc nc nc vdd_ core mcbsp1 _clkx mcbsp2 _dr mcbsp _clks vss nc nc vss nc mcbsp2 _fsx mcbsp1 _dx jtag_tck mcbsp1 _fsr hsusb0 _dir hsusb0 _data0 vdda_ dac cvideo1 _out cvideo1 _vfb vdds vss hsusb0 _data3 hsusb0 _clk hsusb0 _nxt hsusb0 _data4 sys_ clkreq jtag_ emu0 vss hsusb0 _data7 hsusb0 _data5 hsusb0 _data6 hsusb0 _data1 nc vss dss_ data14 uart2 _rts ncnc vdds dss_ data23 dss_ data15 dss_ data10 dss_ data22 vdds nc nc sys_32k vss vdds nc vss nc vdds nc vss i2c4_scl gpio_112 vdds vdds vdds uart2 _rts uart2 _rx uart2 _tx dss_ data4 dss_ data5 vss dss_ data11 pop_y20 _ae25 pop_aa20 _af25 pop_y19 _af24 pop_ aa19_af22 pop_y17 _af21 dss_ data3 dss_ data2 dss_ data0 gpio_114 gpio_115 pop_aa13 _af15 pop_aa14 _af16 pop_y14 _af17 pop_aa17 _af18 sys_ xtalout
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com a. top views are provided to assist in hardware debugging efforts. figure 2-14. cus pin map [quadrant a - top view] 20 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 a 9 8 7 6 5 4 3 2 1 b c d e f g h j k sdrc_a0 nc nc l m gpmc _d0 mcspi2 _cs1 12 11 10 sdrc _dqs0 sdrc _dm2 vdds_x gpmc _ncs3 gpmc _nwp gpmc _nadv _ale gpmc _noe gpmc _a10 gpmc _a8 gpmc _a9 gpmc _a6 gpmc _d2 vdd_mpu _iva vss vss vdd_mpu _iva gpmc_ nbe0_cle vdd_mpu _iva vdd_mpu _iva nc sdrc _dqs2 sdrc _clk sdrc _nclk sdrc_a4 sdrc_a3 sdrc_a1 sdrc_d3 sdrc _dm0 sdrc_d7 sdrc_d18 sdrc_d19 sdrc_d21 sdrc_d8 sdrc_d10 sdrc_d9 sdrc_d20 sdrc_d16 sdrc_d6 sdrc_d2 sdrc_d1 sdrc_a5 gpmc _wait3 gpmc _wait0 sdrc_a2 sdrc_d0 sdrc_d4 sdrc_d5 sdrc_d22 sdrc_d17 sdrc_a8 sdrc_a9 sdrc_a10 sdrc_a6 gpmc _ncs0 gpmc _ncs6 gpmc _ncs4 sdrc_a7 sdrc_a13 sdrc_a14 vdd_ core vdd_mpu _iva sdrc_a12 sdrc_a11 gpmc _ncs5 gpmc _ncs7 gpmc _nwe vdd_mpu _iva vdd_mpu _iva vdd_ core vdd_ core vss vss vdd_mpu _iva vdd_mpu _iva vdds _mem vdds _mem vdds _mem gpmc _a4 gpmc _a5 gpmc _a7 gpmc _a3 gpmc _a2 gpmc _a1 vdds _mem vdds _mem vdds _mem vss vss vdd_mpu _iva vss vss gpmc_ nbe1 gpmc _d1 gpmc _d4 mcspi2 _cs0 vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vss vss
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 2-15. cus pin map [quadrant b - top view] copyright ? 2010 C 2011, texas instruments incorporated terminal description 21 submit documentation feedback product folder link(s): dm3730 dm3725 a 16 17 18 19 20 21 22 23 24 b cam_hs c d e f g h j k dss_ data9 dss_ data19 dss_ acbias l m 13 14 15 sdrc_ dqs1 vdd_ core cam_ xclka uart3_ _cts_ rctx hdq_si0 dss_ data6 dss_ data18 i2c1_sda mmc1_ cmd vdda _dplls _dll cap_vdd _sram _core vdds_ mem cam_vs vdd_ core vss cam_ strobe cam_ pclk vss sdrc_ d14 sdrc_ dm3 sdrc_ dqs3 sdrc_ ncs0 sdrc_ nwe uart3_ _rx_ irrx uart3_ _rts_ sd cam_d5 sdrc_ cke0 sdrc_ ncs1 sdrc_ d31 sdrc_ d30 sdrc_ d27 sdrc_ d15 sdrc_ d13 sdrc_ dm1 sdrc_ d12 sdrc_ d26 sdrc_ d28 sdrc_ ba0 sdrc_ ncas sdrc_ cke1 cam_ xclkb uart3_ _tx_ irtx dss_ data20 sdrc_ nras sdrc_ ba1 sdrc_ d29 sdrc_ d25 sdrc_ d11 sdrc_ d23 sdrc_ d24 vdds dss_ hsync dss_ data7 dss_ data8 dss_ vsync cam_d10 cam_d3 cam_wen vdds_ mem vdds_ mem vdd_ core vdds_ mem vdds_ mem cam_d2 cam_d4 cam_d11 dss_ pclk dss_ data17 cam_fld vdds_ mem vss vdd_ core vss vss vss vss vdd_ core vdd_ core dss_ data16 cam_d8 cam_d7 cam_d9 dss_ data21 i2c1_scl vdd_ core vdd_ core vdd_ core vss vss vss vdd_ core vdd_ core vss cam_d6 mmc1_ clk mmc1_ dat0 mmc1_ dat1 mmc1_ dat2 vdds vdds vss vdd_ core
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 2-16. cus pin map [quadrant c - top view] 22 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 ad 9 etk_d14 8 7 6 5 4 3 2 1 ac ab aa y w v u t r sys_ nres warm vdd_mpu _iva p n gpmc _d3 uart1 _rx 12 11 10 vdd_mpu _iva vss nc uart1 _rts vss mcspi2 _clk mmc2 _dat3 gpmc _d7 gpmc _d8 mcspi2 _simo mcspi1 _cs0 vdd_mpu _iva sys_ clkout1 etk_d4 gpmc _d14 gpmc _clk etk_clk sys_ clkout2 vdds jtag_tms _tmsc vdds_ sram sys_ boot0 uart1_ cts etk_d10 etk_d8 etk_d1 etk_d12 i2c3_sda etk_d0 mcbsp3 _dx mcspi1 _simo mcbsp1 _cs3 cap_vddu_ wkup_logic vdd_mpu _iva vdd_mpu _iva mcspi2 _somi vdd_mpu _iva vss vss vssvss vdd_mpu _iva vssvss vss vss vss gpmc _d11 gpmc _d5 gpmc _d6 vdd_mpu _iva vdd_mpu _iva mcspi1 _clk gpmc _d9 gpmc _d12 mcspi1 _somi vss vss vss vss vss cap_vdd _sram_ mpu_iva gpmc _d13 gpmc _d10 vdd_mpu _iva vdds vdds mcbsp3 _fsx gpmc _d15 mcbsp3 _dr vdd_mpu _iva vdds vdds uart1 _tx mcbsp3 _clkx mmc2 _dat2 vdds mmc2 _dat1 mmc2 _dat6 mmc2 _clk mmc2 _dat7 mmc2 _dat5 jtag_ rtck sys_ nres pwron jtag_ tdi jtag_ tdo jtag_ ntrst jtag_ tck mmc2 _cmd mmc2 _dat0 mmc2 _dat4 etk_d2 etk_d11 etk_d6 etk_d5 etk_ctl etk_d9 etk_d3 etk_d7 etk_d13 etk_d15
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 2-17. cus pin map [quadrant d - top view] copyright ? 2010 C 2011, texas instruments incorporated terminal description 23 submit documentation feedback product folder link(s): dm3730 dm3725 ad 16 17 sys_ xtalin 18 19 20 21 22 23 24 ac dss_ data3 ab aa y w v u t r dss_ data15 dss_ data14 cvideo1 _rset p n 13 14 15 mcbsp1 _clkx vdds vss hsusb0 _stp mmc1_ dat3 gpio_126 cap_vdd _bb_mpu _iva vdd_ core hsusb0 _dir hsusb0 _data0 cvideo2 _out cvideo1 _vfb sys_ clkreq dss_ data23 sys_32k sys_ boot6 vdda_wkup _bg_bb i2c3_scl vssa_dac cam_d0 dss_ data12 sys_off _mode dss_ data10 dss_ data5 dss_ data0 cap_vddu _array sys_ xtalgnd jtag_ emu0 i2c4_scl vssvss vss vss vss vssvss vss vss vss vss vssvss vss vssvss vss vdds vdds vdds_ mmc1 gpio_129 vss hsusb0 _clk mcbsp2 _dx vdd_ core vdd_ core hsusb0 _nxt hsusb0 _data1 hsusb0 _data7 mcbsp2 _clkx vdd_ core vdd_ core vdd_ core vdd_ core hsusb0 _data2 hsusb0 _data3 vdda_ dpll _per vdd_mpu _iva vdd_mpu _iva mcbsp2 _dr mcbsp2 _fsx dss_ data22 hsusb0 _data5 hsusb0 _data6 hsusb0 _data4 mcbsp1 _clkr sys_ nirq mcbsp1 _dx vdd_mpu _iva cvideo2 _vfb dss_ data13 mcbsp1 _dr i2c4_sda mcbsp _clks mcbsp1 _fsx cvideo1 _out mcbsp1 _fsr dss_ data1 sys_ boot5 vdda_ dac i2c2_sda i2c2_scl sys_ boot1 sys_ boot4 cam_d1 dss_ data11 jtag_ emu1 dss_ data4 dss_ data2 sys_ boot3 sys_ boot2 sys_ xtaout
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 2.3 ball characteristics table 2-1 through table 2-3 describe the terminal characteristics and the signals multiplexed on each pin for the cbp, cbc, and cus packages, respectively. the following list describes the table column headers. 1. ball bottom: ball number(s) on the bottom side associated with each signal(s) on the bottom. 2. pin name: names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in mode 0). note : table 2-3 does not take into account subsystem pin multiplexing options. subsystem pin multiplexing options are described in section 2.5 , signal descriptions. 3. mode: multiplexing mode number. ( a) mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin corresponds to the name of the pin. there is always a function mapped on the primary mode. notice that primary mode is not necessarily the default mode. note : the default mode is the mode at the release of the reset; also see the reset rel. mode column. ( b) modes 1 to 7 are possible modes for alternate functions. on each pin, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration. 4. type: signal direction C i = input C o = output C i/o = input/output C d = open drain C ds = differential C a = analog C pwr = power C gnd = ground note : in the safe_mode, the buffer is configured in high-impedance. 5. ball reset state: the state of the terminal at the power-on reset. C 0: the buffer drives v ol (pulldown/pullup resistor not activated) 0(pd): the buffer drives v ol with an active pulldown resistor. C 1: the buffer drives v oh (pulldown/pullup resistor not activated) 1(pu): the buffer drives v oh with an active pullup resistor. C z: high-impedance C l: high-impedance with an active pulldown resistor C h : high-impedance with an active pullup resistor 6. ball reset rel. state: the state of the terminal at the release of the system control module reset (prcm core_rstpwron_ret reset signal). C 0: the buffer drives v ol (pulldown/pullup resistor not activated) 0(pd): the buffer drives v ol with an active pulldown resistor. C 1: the buffer drives v oh (pulldown/pullup resistor not activated) 1(pu): the buffer drives v oh with an active pullup resistor. C z: high-impedance C l: high-impedance with an active pulldown resistor C h : high-impedance with an active pullup resistor 7. reset rel. mode: the mode is automatically configured at the release of the system control module reset (prcm core_rstpwron_ret reset signal). 8. power: the voltage supply that powers the terminal s i/o buffers. 9. hys: indicates if the input buffer is with hysteresis. 10. buffer strength: drive strength of the associated output buffer. 24 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 11. pull u/d - type: denotes the presence of an internal pullup or pulldown resistor. pullup and pulldown resistors can be enabled or disabled via software. note : the pullup/pulldown drive strength is equal to minimum = 50 a, typical = 100 a, maximum = 250 a (unless otherwise specified), except for cbp balls p27, p26, r27, and r25, and cus balls n22 and p24, where the pulldown drive strength is equal to 1.8 k ? . 12. io cell: io cell information. note : configuring two pins to the same input signal is not supported as it can yield unexpected results. this can be easily prevented with the proper software configuration. note in the dm3730/25 device, new far end load settings registers are added for some ios. this new feature configures the io according to the transmission line and the application/peripheral load. for a full description on these registers, see the system control module / scm functional description / functional register description / signal integrity parameter control registers with pad group assignment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-1. ball characteristics (cbp pkg.) (3) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] na j2 sdrc_d0 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na j1 sdrc_d1 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na g2 sdrc_d2 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na g1 sdrc_d3 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na f2 sdrc_d4 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na f1 sdrc_d5 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na d2 sdrc_d6 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na d1 sdrc_d7 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b13 sdrc_d8 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a13 sdrc_d9 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b14 sdrc_d10 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a14 sdrc_d11 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b16 sdrc_d12 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a16 sdrc_d13 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b19 sdrc_d14 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a19 sdrc_d15 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b3 sdrc_d16 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a3 sdrc_d17 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b5 sdrc_d18 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a5 sdrc_d19 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b8 sdrc_d20 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a8 sdrc_d21 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b9 sdrc_d22 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a9 sdrc_d23 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b21 sdrc_d24 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na a21 sdrc_d25 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na d22 sdrc_d26 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na d23 sdrc_d27 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na e22 sdrc_d28 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na e23 sdrc_d29 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na g22 sdrc_d30 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na g23 sdrc_d31 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na ab21 sdrc_ba0 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na ac21 sdrc_ba1 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 25 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] na n22 sdrc_a0 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na n23 sdrc_a1 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na p22 sdrc_a2 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na p23 sdrc_a3 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na r22 sdrc_a4 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na r23 sdrc_a5 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na t22 sdrc_a6 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na t23 sdrc_a7 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na u22 sdrc_a8 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na u23 sdrc_a9 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na v22 sdrc_a10 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na v23 sdrc_a11 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na w22 sdrc_a12 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na w23 sdrc_a13 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na y22 sdrc_a14 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na m22 sdrc_ncs0 0 o 1 1 0 vdds_mem no 4 (12) na lvcmos na m23 sdrc_ncs1 0 o 1 1 0 vdds_mem no 4 (12) na lvcmos na a11 sdrc_clk 0 io l 0 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b11 sdrc_nclk 0 o 1 1 0 vdds_mem no 4 (12) na lvcmos na j22 sdrc_cke0 0 o h 1 7 vdds_mem yes 4 (12) pu/ pd lvcmos safe_mode_out1 (13) 7 na j23 sdrc_cke1 0 o h 1 7 vdds_mem na 4 (12) pu/ pd lvcmos safe_mode_out1 (13) 7 na l23 sdrc_nras 0 o 1 1 0 vdds_mem no 4 (12) na lvcmos na l22 sdrc_ncas 0 o 1 1 0 vdds_mem no 4 (12) na lvcmos na k23 sdrc_nwe 0 o 1 1 0 vdds_mem no 4 (12) na lvcmos na c1 sdrc_dm0 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na a17 sdrc_dm1 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na a6 sdrc_dm2 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na a20 sdrc_dm3 0 o 0 0 0 vdds_mem no 4 (12) na lvcmos na c2 sdrc_dqs0 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b17 sdrc_dqs1 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b6 sdrc_dqs2 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos na b20 sdrc_dqs3 0 io l z 0 vdds_mem yes 4 (12) pu/ pd lvcmos n4 ac15 gpmc_a1 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_34 4 io safe_mode 7 m4 ab15 gpmc_a2 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_35 4 io safe_mode 7 l4 ac16 gpmc_a3 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_36 4 io safe_mode 7 k4 ab16 gpmc_a4 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_37 4 io safe_mode 7 t3 ac17 gpmc_a5 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_38 4 io safe_mode 7 r3 ab17 gpmc_a6 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpio_39 4 io safe_mode 7 26 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] n3 ac18 gpmc_a7 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpio_40 4 io safe_mode 7 m3 ab18 gpmc_a8 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpio_41 4 io safe_mode 7 l3 ac19 gpmc_a9 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq2 1 i gpio_42 4 io safe_mode 7 k3 ab19 gpmc_a10 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq3 1 i gpio_43 4 io safe_mode 7 na ac20 gpmc_a11 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos safe_mode 7 k1 m2 gpmc_d0 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos l1 m1 gpmc_d1 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos l2 n2 gpmc_d2 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos p2 n1 gpmc_d3 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos t1 r2 gpmc_d4 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos v1 r1 gpmc_d5 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos v2 t2 gpmc_d6 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos w2 t1 gpmc_d7 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos h2 ab3 gpmc_d8 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_44 4 io safe_mode 7 k2 ac3 gpmc_d9 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_45 4 io safe_mode 7 p1 ab4 gpmc_d10 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_46 4 io safe_mode 7 r1 ac4 gpmc_d11 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_47 4 io safe_mode 7 r2 ab6 gpmc_d12 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_48 4 io safe_mode 7 t2 ac6 gpmc_d13 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_49 4 io safe_mode 7 w1 ab7 gpmc_d14 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_50 4 io safe_mode 7 y1 ac7 gpmc_d15 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_51 4 io safe_mode 7 g4 y2 gpmc_ncs0 0 o 1 1 0 vdds_mem na 8 na lvcmos h3 y1 gpmc_ncs1 0 o h 1 0 vdds_mem yes 8 pu/ pd lvcmos gpio_52 4 io safe_mode 7 copyright ? 2010 C 2011, texas instruments incorporated terminal description 27 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] v8 na gpmc_ncs2 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpio_53 4 io safe_mode 7 u8 na gpmc_ncs3 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq0 1 i gpio_54 4 io safe_mode 7 t8 na gpmc_ncs4 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq1 1 i mcbsp4_clkx 2 io gpt_9_pwm_evt 3 io gpio_55 4 io safe_mode 7 r8 na gpmc_ncs5 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq2 1 i mcbsp4_dr 2 i gpt_10_pwm_evt 3 io gpio_56 4 io safe_mode 7 p8 na gpmc_ncs6 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq3 1 i mcbsp4_dx 2 io gpt_11_pwm_evt 3 io gpio_57 4 io safe_mode 7 n8 na gpmc_ncs7 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpmc_io_dir 1 o mcbsp4_fsx 2 io gpt_8_pwm_evt 3 io gpio_58 4 io safe_mode 7 t4 w2 gpmc_clk 0 o l 0 0 vdds_mem yes 8 pu/ pd lvcmos gpio_59 4 io safe_mode 7 f3 w1 gpmc_nadv_ale 0 o 0 0 0 vdds_mem na 8 pu/ pd lvcmos g2 v2 gpmc_noe 0 o 1 1 0 vdds_mem na 8 pu/ pd lvcmos f4 v1 gpmc_nwe 0 o 1 1 0 vdds_mem na 8 pu/ pd lvcmos g3 ac12 gpmc_nbe0_cle 0 o l 0 0 vdds_mem yes 8 pu/ pd lvcmos gpio_60 4 io safe_mode 7 u3 na gpmc_nbe1 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_61 4 io safe_mode 7 h1 ab10 gpmc_nwp 0 o l 0 0 vdds_mem yes 8 pu/ pd lvcmos gpio_62 4 io safe_mode 7 m8 ab12 gpmc_wait0 0 i h h 0 vdds_mem yes na pu/ pd lvcmos l8 ac10 gpmc_wait1 0 i h h 7 vdds_mem yes 8 pu/ pd lvcmos gpio_63 4 io safe_mode 7 k8 na gpmc_wait2 0 i h h 7 vdds_mem yes 8 pu/ pd lvcmos uart4_tx 2 o gpio_64 4 io safe_mode 7 28 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] j8 na gpmc_wait3 0 i h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq1 1 i uart4_rx 2 i gpio_65 4 io safe_mode 7 d28 na dss_pclk 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_66 4 io hw_dbg12 5 o safe_mode 7 d26 na dss_hsync 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_67 4 io hw_dbg13 5 o safe_mode 7 d27 na dss_vsync 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_68 4 io safe_mode 7 e27 na dss_acbias 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_69 4 io safe_mode 7 ag22 na dss_data0 0 io l l 7 vdd s yes 8 pu/ pd lvcmos uart1_cts 2 i na gpio_70 4 io 8 safe_mode 7 8 ah22 na dss_data1 0 io l l 7 vdd s yes 8 pu/ pd lvcmos uart1_rts 2 o 8 gpio_71 4 io 8 safe_mode 7 8 ag23 na dss_data2 0 io l l 7 vdd s yes 8 pu/ pd lvcmos gpio_72 4 io 8 safe_mode 7 8 ah23 na dss_data3 0 io l l 7 vdd s yes 8 pu/ pd lvcmos gpio_73 4 io 8 safe_mode 7 8 ag24 na dss_data4 0 io l l 7 vdd s yes 8 pu/ pd lvcmos uart3_rx_irrx 2 i na gpio_74 4 io 8 safe_mode 7 8 ah24 na dss_data5 0 io l l 7 vdd s yes 8 pu/ pd lvcmos uart3_tx_irtx 2 o 8 gpio_75 4 io 8 safe_mode 7 8 e26 na dss_data6 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_tx 2 o gpio_76 4 io hw_dbg14 5 o safe_mode 7 f28 na dss_data7 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_rx 2 i gpio_77 4 io hw_dbg15 5 o safe_mode 7 copyright ? 2010 C 2011, texas instruments incorporated terminal description 29 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] f27 na dss_data8 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart3_rx_irrx 2 i gpio_78 4 io hw_dbg16 5 o safe_mode 7 g26 na dss_data9 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart3_tx_irtx 2 o gpio_79 4 io hw_dbg17 5 o safe_mode 7 ad28 na dss_data10 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_80 4 io safe_mode 7 ad27 na dss_data11 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_81 4 io safe_mode 7 ab28 na dss_data12 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_82 4 io safe_mode 7 ab27 na dss_data13 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_83 4 io safe_mode 7 aa28 na dss_data14 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_84 4 io safe_mode 7 aa27 na dss_data15 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_85 4 io safe_mode 7 g25 na dss_data16 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_86 4 io safe_mode 7 h27 na dss_data17 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_87 4 io safe_mode 7 h26 na dss_data18 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_clk 2 io dss_data0 3 io gpio_88 4 io safe_mode 7 h25 na dss_data19 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_simo 2 io dss_data1 3 io gpio_89 4 io safe_mode 7 e28 na dss_data20 0 o h h 7 vdds yes 8 pu/ pd lvcmos mcspi3_somi 2 io dss_data2 3 io gpio_90 4 io safe_mode 7 j26 na dss_data21 0 o l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_cs0 2 io dss_data3 3 io gpio_91 4 io safe_mode 7 30 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] ac27 na dss_data22 0 o l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_cs1 2 o dss_data4 3 io gpio_92 4 io safe_mode 7 ac28 na dss_data23 0 o l l 7 vdds yes 8 pu/ pd lvcmos dss_data5 3 io gpio_93 4 io safe_mode 7 w28 na cvideo2_out 0 ao 0 0 0 vdda_dac na na (4) na 10-bit dac y28 na cvideo1_out 0 ao 0 0 0 vdda_dac na na (4) na 10-bit dac y27 na cvideo1_vfb 0 ao 0 na 0 vdda_dac na na (10) na 10-bit dac w27 na cvideo2_vfb 0 ao 0 na 0 vdda_dac na na (10) na 10-bit dac w26 na cvideo1_rset 0 aio 0 na 0 vdda_dac no na na 10-bit dac a24 na cam_hs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_94 4 io hw_dbg0 5 o safe_mode 7 a23 na cam_vs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_95 4 io hw_dbg1 5 o safe_mode 7 c25 na cam_xclka 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_96 4 io safe_mode 7 c27 na cam_pclk 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_97 4 io hw_dbg2 5 o safe_mode 7 c23 na cam_fld 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io gpio_98 4 io hw_dbg3 5 o safe_mode 7 ag17 na cam_d0 0 i l l 7 vdds yes na pu/pd lvcmos gpio_99 4 i safe_mode 7 ah17 na cam_d1 0 i l l 7 vdds yes na pu/pd lvcmos gpio_100 4 i safe_mode 7 b24 na cam_d2 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_101 4 io hw_dbg4 5 o safe_mode 7 c24 na cam_d3 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_102 4 io hw_dbg5 5 o safe_mode 7 d24 na cam_d4 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_103 4 io hw_dbg6 5 o safe_mode 7 a25 na cam_d5 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_104 4 io copyright ? 2010 C 2011, texas instruments incorporated terminal description 31 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] hw_dbg7 5 o safe_mode 7 k28 na cam_d6 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_105 4 i safe_mode 7 l28 na cam_d7 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_106 4 i safe_mode 7 k27 na cam_d8 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_107 4 i safe_mode 7 l27 na cam_d9 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_108 4 i safe_mode 7 b25 na cam_d10 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_109 4 io hw_dbg8 5 o safe_mode 7 c26 na cam_d11 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_110 4 io hw_dbg9 5 o safe_mode 7 b26 na cam_xclkb 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_111 4 io safe_mode 7 b23 na cam_wen 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_shutter 2 o gpio_167 4 io hw_dbg10 5 o safe_mode 7 d25 na cam_strobe 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_126 4 io hw_dbg11 5 o safe_mode 7 ag19 na gpio_112 4 i l l 7 vdds yes na pu/pd lvcmos safe_mode 7 ah19 na gpio_113 4 i l l 7 vdds yes na pu/pd lvcmos safe_mode 7 ag18 na gpio_114 4 i l l 7 vdds yes na pu/pd lvcmos safe_mode 7 - ah18 na gpio_115 4 i l l 7 vdds yes na pu/pd lvcmos safe_mode 7 - p21 na mcbsp2_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_116 4 io safe_mode 7 n21 na mcbsp2_clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_117 4 io safe_mode 7 r21 na mcbsp2_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_118 4 io safe_mode 7 m21 na mcbsp2_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_119 4 io safe_mode 7 32 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] n28 na mmc1_clk 0 o l l 7 vdds_mmc1 ( yes 1 pu/ pd (5) lvcmos 15) gpio_120 (1) 4 io safe_mode 7 m27 na mmc1_cmd 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (5) lvcmos 15) gpio_121 (1) 4 io safe_mode 7 n27 na mmc1_dat0 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (5) lvcmos 15) gpio_122 (1) 4 io safe_mode 7 n26 na mmc1_dat1 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (5) lvcmos 15) gpio_123 (1) 4 io safe_mode 7 n25 na mmc1_dat2 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (5) lvcmos 15) gpio_124 (1) 4 io safe_mode 7 p28 na mmc1_dat3 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (5) lvcmos 15) gpio_125 (1) 4 io safe_mode 7 p27 na gpio_126 (1) 4 io l l 7 vdds _x yes 1 pu/ pd (5) lvcmos safe_mode 7 p26 na gpio_127 (1) 4 io l l 7 vdds _x yes 1 pu/ pd (5) lvcmos safe_mode 7 r27 na gpio_128 4 io l l 7 vdds yes 4 pu/ pd lvcmos safe_mode 7 r25 na gpio_129 (1) 4 io l l 7 vdds _x yes 1 pu/ pd (5) lvcmos safe_mode 7 ae2 na mmc2_clk 0 o l l 7 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io gpio_130 4 io safe_mode 7 ag5 na mmc2_cmd 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_simo 1 io gpio_131 4 io safe_mode 7 ah5 na mmc2_dat0 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_somi 1 io gpio_132 4 io safe_mode 7 ah4 na mmc2_dat1 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_133 4 io safe_mode 7 ag4 na mmc2_dat2 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o gpio_134 4 io safe_mode 7 af4 na mmc2_dat3 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io gpio_135 4 io safe_mode 7 ae4 na mmc2_dat4 0 io l l 7 vdds yes 4 pu/ pd lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 33 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] mmc2_dir_dat0 1 o mmc3_dat0 3 io gpio_136 4 io safe_mode 7 ah3 na mmc2_dat5 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat1 1 o cam_global_reset 2 io mmc3_dat1 3 io gpio_137 4 io mm3_rxdp 6 io safe_mode 7 af3 na mmc2_dat6 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_cmd 1 o cam_shutter 2 o mmc3_dat2 3 io gpio_138 4 io safe_mode 7 ae3 na mmc2_dat7 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_clkin 1 i mmc3_dat3 3 io gpio_139 4 io mm3_rxdm 6 io safe_mode 7 af6 na mcbsp3_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_cts 1 i gpio_140 4 io safe_mode 7 ae6 na mcbsp3_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos uart2_rts 1 o gpio_141 4 io safe_mode 7 af5 na mcbsp3_clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_tx 1 o gpio_142 4 io safe_mode 7 ae5 na mcbsp3_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_rx 1 i gpio_143 4 io safe_mode 7 ab26 na uart2_cts 0 i h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_dx 1 io gpt_9_pwm_evt 2 io gpio_144 4 io safe_mode 7 ab25 na uart2_rts 0 o h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_dr 1 i gpt_10_pwm_evt 2 io gpio_145 4 io safe_mode 7 aa25 na uart2_tx 0 o h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_clkx 1 io gpt_11_pwm_evt 2 io gpio_146 4 io safe_mode 7 34 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] ad25 na uart2_rx 0 i h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_fsx 1 io gpt_8_pwm_evt 2 io gpio_147 4 io safe_mode 7 aa8 na uart1_tx 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_148 4 io safe_mode 7 aa9 na uart1_rts 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_149 4 io safe_mode 7 w8 na uart1_cts 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_150 4 io safe_mode 7 y8 na uart1_rx 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcbsp1_clkr 2 io mcspi4_clk 3 io gpio_151 4 io safe_mode 7 ae1 na mcbsp4_clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_152 4 io mm3_txse0 6 io safe_mode 7 ad1 na mcbsp4_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_153 4 io mm3_rxrcv 6 io safe_mode 7 ad2 na mcbsp4_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_154 4 io mm3_txdat 6 io safe_mode 7 ac1 na mcbsp4_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_155 4 io mm3_txen_n 6 io safe_mode 7 y21 na mcbsp1_clkr 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_clk 1 io gpio_156 4 io safe_mode 7 aa21 na mcbsp1_fsr 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io gpio_157 4 io safe_mode 7 v21 na mcbsp1_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_simo 1 io mcbsp3_dx 2 io gpio_158 4 io safe_mode 7 u21 na mcbsp1_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_somi 1 io mcbsp3_dr 2 i gpio_159 4 io safe_mode 7 t21 na mcbsp_clks 0 i l l 7 vdds yes 4 pu/ pd lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 35 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] cam_shutter 2 o gpio_160 4 io uart1_cts 5 i safe_mode 7 k26 na mcbsp1_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_cs0 1 io mcbsp3_fsx 2 io gpio_161 4 io safe_mode 7 w21 na mcbsp1_clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcbsp3_clkx 2 io gpio_162 4 io safe_mode 7 h18 na uart3_cts_rctx 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_163 4 io safe_mode 7 h19 na uart3_rts_sd 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_164 4 io safe_mode 7 h20 na uart3_rx_irrx 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_165 4 io safe_mode 7 h21 na uart3_tx_irtx 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_166 4 io safe_mode 7 t28 na hsusb0_clk 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_120 4 io safe_mode 7 t25 na hsusb0_stp 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_121 4 io safe_mode 7 r28 na hsusb0_dir 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_122 4 io safe_mode 7 t26 na hsusb0_nxt 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_124 4 io safe_mode 7 t27 na hsusb0_data0 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_tx_irtx 2 o gpio_125 4 io uart2_tx 5 o safe_mode 7 u28 na hsusb0_data1 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rx_irrx 2 i gpio_130 4 io uart2_rx 5 i safe_mode 7 u27 na hsusb0_data2 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rts_sd 2 o gpio_131 4 io uart2_rts 5 o safe_mode 7 u26 na hsusb0_data3 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_cts_rctx 2 io 36 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] gpio_169 4 io uart2_cts 5 i safe_mode 7 u25 na hsusb0_data4 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_188 4 io safe_mode 7 v28 na hsusb0_data5 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_189 4 io safe_mode 7 v27 na hsusb0_data6 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_190 4 io safe_mode 7 v26 na hsusb0_data7 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_191 4 io safe_mode 7 k21 na i2c1_scl 0 od h h 0 vdds na 3 pu/ pd (6) (7) open drain j21 na i2c1_sda 0 iod h h 0 vdds yes 3 pu/ pd (6) (7) open drain af15 na i2c2_scl 0 od h h 7 vdds yes 3 pu/ pd (6) (8) open drain gpio_168 4 io 4 safe_mode 7 ae15 na i2c2_sda 0 iod h h 7 vdds yes 3 pu/ pd (6) (8) open drain gpio_183 4 io 4 safe_mode 7 af14 na i2c3_scl 0 od h h 7 vdds yes 3 pu/ pd (6) (8) open drain gpio_184 4 io 4 safe_mode 7 ag14 na i2c3_sda 0 iod h h 7 vdds yes 3 pu/ pd (6) (8) open drain gpio_185 4 io 4 safe_mode 7 ad26 na i2c4_scl 0 od h h 0 vdds yes 3 pu/ pd (6) (7) open drain sys_ nvmode1 1 o 4 safe_mode 7 ae26 na i2c4_sda 0 iod h h 0 vdds yes 3 pu/ pd (6) (7) open drain sys_ nvmode2 1 o 4 safe_mode 7 j25 na hdq_sio 0 iod h h 7 vdds yes 4 pu/ pd lvcmos sys_altclk 1 i i2c2_sccbe 2 od i2c3_sccbe 3 od gpio_170 4 io safe_mode 7 ab3 na mcspi1_clk 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat4 1 io gpio_171 4 io safe_mode 7 ab4 na mcspi1_ simo 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat5 1 io gpio_172 4 io safe_mode 7 aa4 na mcspi1_ somi 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat6 1 io gpio_173 4 io safe_mode 7 ac2 na mcspi1_cs0 0 io h h 7 vdds yes 4 pu/ pd lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 37 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] mmc2_dat7 1 io gpio_174 4 io safe_mode 7 ac3 na mcspi1_cs1 0 o h h 7 vdds yes 4 pu/ pd lvcmos mmc3_cmd 3 io gpio_175 4 io safe_mode 7 ab1 na mcspi1_cs2 0 o h h 7 vdds yes 4 pu/ pd lvcmos mmc3_clk 3 o gpio_176 4 io safe_mode 7 ab2 na mcspi1_cs3 0 o h h 7 vdds yes 4 pu/ pd lvcmos hsusb2_ data2 3 io gpio_177 4 io mm2_txdat 5 io safe_mode 7 aa3 na mcspi2_clk 0 io l l 7 vdds yes 4 pu/ pd lvcmos hsusb2_ data7 3 io gpio_178 4 io safe_mode 7 y2 na mcspi2_ simo 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt_9_pwm_evt 1 io hsusb2_ data4 3 io gpio_179 4 io safe_mode 7 y3 na mcspi2_ somi 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt_10_pwm_evt 1 io hsusb2_ data5 3 io gpio_180 4 io safe_mode 7 y4 na mcspi2_cs0 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpt_11_pwm_evt 1 io hsusb2_ data6 3 io gpio_181 4 io safe_mode 7 v3 na mcspi2_cs1 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpt_8_pwm_evt 1 io hsusb2_ data3 3 io gpio_182 4 io mm2_txen_n 5 io safe_mode 7 ae25 na sys_32k 0 i z z 0 vdds yes na pu/ pd lvcmos ae17 na sys_xtalin 0 ai z z 0 vdds yes na no lvcmos analog af17 na sys_xtalout 0 ao z 0 0 vdds na na na lvcmos analog af25 na sys_clkreq 0 io 0 see (11) 0 vdds yes 4 pu/ pd lvcmos gpio_1 4 io safe_mode 7 af26 na sys_nirq 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_0 4 io safe_mode 7 ah25 na sys_nrespwron 0 i z z 0 vdds yes na no lvcmos af24 na sys_nreswarm 0 iod 0 h 0 vdds yes 4 pu/ pd lvcmos gpio_30 4 io open drain 38 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] safe_mode 7 ah26 na sys_boot0 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data18 3 io gpio_2 4 io safe_mode 7 ag26 na sys_boot1 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data19 3 io gpio_3 4 io safe_mode 7 ae14 na sys_boot2 0 i z z 0 vdds yes 8 pu/ pd lvcmos gpio_4 4 io safe_mode 7 af18 na sys_boot3 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data20 3 o gpio_5 4 io safe_mode 7 af19 na sys_boot4 0 i z z 0 vdds yes 8 pu/ pd lvcmos mmc2_dir_dat2 1 o dss_data21 3 o gpio_6 4 io safe_mode 7 ae21 na sys_boot5 0 i z z 0 vdds yes 8 pu/ pd lvcmos mmc2_dir_dat3 1 o dss_data22 3 o gpio_7 4 io safe_mode 7 af21 na sys_boot6 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data23 3 o gpio_8 4 io safe_mode 7 af22 na sys_off_mode 0 o 0 l 7 vdds yes 4 pu/ pd lvcmos gpio_9 4 io safe_mode 7 ag25 na sys_clkout1 0 o l l 7 (14) vdds yes 4 pu/ pd lvcmos gpio_10 4 io safe_mode 7 ae22 na sys_clkout2 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_186 4 io safe_mode 7 aa17 na jtag_ntrst 0 i l l 0 vdds yes na pu/ pd lvcmos aa13 na jtag_tck 0 i l l 0 vdds yes na pu/ pd lvcmos aa12 na jtag_rtck 0 o l 0 0 vdds na 4 pu/ pd lvcmos aa18 na jtag_tms_tmsc 0 io h h 0 vdds yes 4 pu/ pd lvcmos aa20 na jtag_tdi 0 i h h 0 vdds yes na pu/ pd lvcmos aa19 na jtag_tdo 0 o l z 0 vdds na 4 pu/ pd lvcmos aa11 na jtag_emu0 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_11 4 io safe_mode 7 aa10 na jtag_emu1 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_31 4 io safe_mode 7 af10 na etk_clk 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcbsp5_ clkx 1 io mmc3_clk 2 o copyright ? 2010 C 2011, texas instruments incorporated terminal description 39 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] hsusb1_stp 3 o gpio_12 4 io mm1_rxdp 5 io hw_dbg0 7 o ae10 na etk_ctl 0 o h h 4 vdds yes 4 pu/ pd lvcmos mmc3_cmd 2 io hsusb1_clk 3 o gpio_13 4 io hw_dbg1 7 o af11 na etk_d0 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_ simo 1 io mmc3_dat4 2 io hsusb1_ data0 3 io gpio_14 4 io mm1_rxrcv 5 io hw_dbg2 7 o ag12 na etk_d1 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 1 io hsusb1_ data1 3 io gpio_15 4 io mm1_txse0 5 io hw_dbg3 7 o ah12 na etk_d2 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io hsusb1_ data2 3 io gpio_16 4 io mm1_txdat 5 io hw_dbg4 7 o ae13 na etk_d3 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io mmc3_dat3 2 io hsusb1_ data7 3 io gpio_17 4 io hw_dbg5 7 o ae11 na etk_d4 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dr 1 i mmc3_dat0 2 io hsusb1_ data4 3 io gpio_18 4 io hw_dbg6 7 o ah9 na etk_d5 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_fsx 1 io mmc3_dat1 2 io hsusb1_ data5 3 io gpio_19 4 io hw_dbg7 7 o af13 na etk_d6 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dx 1 o mmc3_dat2 2 io hsusb1_ data6 3 io gpio_20 4 io hw_dbg8 7 o ah14 na etk_d7 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o 40 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] mmc3_dat7 2 io hsusb1_ data3 3 io gpio_21 4 io mm1_txen_n 5 io hw_dbg9 7 o af9 na etk_d8 0 o l l 4 vdds yes 4 pu/ pd lvcmos mmc3_dat6 2 io hsusb1_dir 3 i gpio_22 4 io hw_dbg10 7 o ag9 na etk_d9 0 o l l 4 vdds yes 4 pu/ pd lvcmos mmc3_dat5 2 io hsusb1_nxt 3 i gpio_23 4 io mm1_rxdm 5 io hw_dbg11 7 o ae7 na etk_d10 0 o l l 4 vdds yes 4 pu/ pd lvcmos uart1_rx 2 i hsusb2_clk 3 o gpio_24 4 io hw_dbg12 7 o af7 na etk_d11 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_stp 3 o gpio_25 4 io mm2_rxdp 5 io hw_dbg13 7 o ag7 na etk_d12 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_dir 3 i gpio_26 4 io hw_dbg14 7 o ah7 na etk_d13 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_nxt 3 i gpio_27 4 io mm2_rxdm 5 io hw_dbg15 7 o ag8 na etk_d14 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_ data0 3 io gpio_28 4 io mm2_rxrcv 5 io hw_dbg16 7 o ah8 na etk_d15 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_ data1 3 io gpio_29 4 io mm2_txse0 5 io hw_dbg17 7 o ah21 na vss 0 gnd - - - - - - - - ag16 na vss 0 gnd - - - - - - - - m28 na vss 0 gnd - - - - - - - - ah20 na cap_vddu_array 0 pwr - - - - - - - - ag20 na vdds 0 pwr - - - - - - - - ag21 na vdd s 0 pwr - - - - - - - - h28 na vdds 0 pwr - - - - - - - - p25 na vdds _x 0 pwr - - - - - - - - copyright ? 2010 C 2011, texas instruments incorporated terminal description 41 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] ae9, ae18, na vdd_core 0 pwr - - - - - - - - ae19, ae24, ac4, y16, y18, y19, y20, w18, w20, v20, u19, u20, t19, p20, n19, n20, m19, m25, l25, k18, k20, j4, j18, j19, j20, h4, e25, d8, d9, d15, d22, d23 y9, y10, na vdd_mpu_iva 0 pwr - - - - - - - - y11, y14, y15, w9, w11, w12, w15, u10, t9, t10, r9, r10, n10, m9, m10, l9, l10, k11, k14, k13, j9, j10, j11, j14, j15 ah6, u1, ac5, p1, vdds_mem 0 pwr - - - - - - - - r4, j1, j2, h1, f23, e1, g28, f1, f2, c23, a4, a7, d16, c16, a10, a15, c28, b5, b8, a18 b12, b18, b22, a5, a8, a12, a18, a22 ag27, af8, na vdds 0 pwr - - - - - - - - af16, af23, ae8, ae16, ae23, ad3, ad4, w4, f25, f26 w16 na vdds_sram 0 pwr k15 na vdda_dplls_dll 0 pwr - - - - - - - - aa16 na vdda_dpll_per 0 pwr - - - - - - - - aa14 na vdda_wkup_ 0 pwr - - - - - - - - bg_bb k25 na vdds_mmc1 0 pwr - - - - - - - - v25 na vdda_dac 0 pwr - - - - - - - - y26 na vssa_dac 0 gnd - - - - - - - - 42 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] ag2, ag3, b4, b7, b10, vss 0 gnd - - - - - - - - ag6, af12, b15, b18, af20, ae12, c22, e2, ae20, f22, h2, p2, ac25, ab5, ab14, ac26, y12, ab20 y13, y25, w3, w10, w13, w14, w17, w19, w25, v9, v10, v19, u2, u9, t20, r19, r20, r26, p3, p4, p9, p10, p19, n9, m20, l19, l20, l26, k9, k10, k12, k16, k17, k19, j3, j12, j13, j16, j17, g27, e3,e4, d7, d10, d13, d19, d21, c7, c10, c13, c19, c22, b2, b27, a3, a26 aa15 na cap_vddu_wkup_ 0 pwr - - - - - - - - logic ah10, a12, aa1, feed-through - - - - - - - - - - ah11, aa23, ab11, pins (9) ah13, ab9, ac11, ah15, ac13, ah16, ac14, ac8, ag11, ac9, h23, ag13, af1, k1, l1, u1, af28, ae28, y23, a1, a2, aa1, n1, a22, a23, m1, j28, ab1, ab23, a15, m2, ac1, ac2, n2, a1, a2, ac22, a27, a28, ac23, b1, ag1, ag28, b23, aa2, ah1, ah2, u2, aa22, ah27, ab8, ab13, ah28, b1, b12, h22, b28, aa2, k2, k22, l2 af2, af27, ag10, ag15, b15, j27, m26 copyright ? 2010 C 2011, texas instruments incorporated terminal description 43 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-1. ball characteristics (cbp pkg.) (3) (continued) ball ball ball reset buffer pullup ball top reset io cell bottom pin name [2] mode [3] type [4] reset rel. mode power [8] hys [9] strength /down [1] rel. [12] [1] state [5] [7] (ma) [10] type [11] state [6] g1, a13, ab2, ab22, no connect (2) - - a14,a16, b2, b22 a17, b14, b16, b17, c14, c15, c17, d17, d18, h9, h10, h11, h12, h13, h14, h15, h16, h17, a4, a6, a7, a9, a10, a11, a19, a20, a21, b3, b4, b6, b7, b9, b10, b11, b13, b19, b20, b21, c1,c2, c3, c4,c5, c6, c8,c9, c11, c12, c18, c20, c21, d1, d2, d3, d4, d5,d6, d11, d12,d14, d20, e1,e2, aa26, ae27 y17 na sys_xtalgnd 0 gnd u4 na cap_vdd_bb_ 0 pwr mpu_iva v4 na cap_vdd_sram 0 pwr _mpu_iva l21 na cap_vdd_sram_core 0 pwr (1) the usage of this gpio is strongly restricted. for more information, see the gpio chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (2) pins labeled as "no connect" must be left unconnected. any connections to these pins may result in unpredictable behavior. (3) na in this table stands for "not applicable". (4) the drive strength is fixed regardless of the load. the driver is designed to drive 75-ohm for video applications. (5) pu = [50 to 100 k ] per default or [10 to 50 k ] according to the selected mode. for a full description of the pull-up drive strength programming, see the prg_sdmmc_pustrength configuration register bit field in the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). pd: 30 to 150 k . (6) the pullup and pulldown can be either the standard lvcmos 100- a drive strength or the i2c pullup and pulldown described below: nominal resistance = 1.66 k in high-speed mode with a load range of 5 pf to 12 pf, 4.5 k in standard / fast mode with a load range of 5 pf to 15 pf. (7) the default buffer configuration is high-speed i2c point-to-point mode using internal pullup. for a full description of the pull drive strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the control_prog_io1, control_prog_io_wkup1 control modules in the system control module / scm programming model / feature settings section and the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) to modify the io settings if required by the targeted interface application. (8) the default buffer configuration is standard lvcmos mode (non-i2c). for a full description of the pull drive strength programming, see padconfs bits of control_padconf_x control modules (standard lvcmos mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the control_prog_io2, control_prog_io3 control modules (i2c mode) in the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) to modify the io settings if required by the targeted interface application. (9) these signals are feed-through balls. for more information, see table 2-28 . (10) in buffer mode, the drive strength is fixed regardless of the load. the driver is designed to drive 75 for video applications. in bypass mode, the drive strength is 0.47 ma. (11) depending on the sys_clkreq direction the corresponding reset released state value can be: C z if sys_clkreq is used as input C 1 if sys_clkreq is used as output for a full description of the sys_clkreq control, see power, reset, and clock management chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (12) the drive strength of these ios is set according to the programmable load range: 2 pf to 4 pf per default or 4 pf to 12 pf. for a full description of the drive strength programming, see the system control module chapter of the am/dm37x multimedia device technical 44 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 reference manual (literature number sprugn4 ). (13) in the safe_mode_out1, the buffer is configured to drive 1. (14) mux0 if sys_boot6 is pulled down (clock master). (15) if mmc1 functional signals are enabled, vdds_mmc1 for mmc1 must be supplied by a dedicated power source. if mmc1 functional signals are disabled, other multiplexed cmos signals of the interface can be enabled. the interface can be supplied by the same power source as vdds. the vdds power source supplies the vdds_mmc1 ball. if neither mmc1 functional balls or cmos signals are enabled, the interface balls are left unconnected with its associated power supply (vdda/vssa) grounded. for the corresponding setting of the pbiaslitepwrdnz0 bit, see the system control module / scm programming model / extended-drain i/os and pbias cells programming guide section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-2. ball characteristics (cbc pkg.) (5) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] ae16 na cam_d0 0 i l l 7 vdda yes na pu/ pd lvcmos gpio_99 4 i safe_mode 7 - ae15 na cam_d1 0 i l l 7 vdda yes na pu/ pd lvcmos gpio_100 4 i safe_mode 7 - ad17 na gpio_112 4 i l l 7 vdda yes na pu/ pd lvcmos safe_mode 7 - ae18 na gpio_114 4 i l l 7 vdda yes na pu/ pd lvcmos safe_mode 7 - ad16 na gpio_113 4 i l l 7 vdda yes na pu/ pd lvcmos safe_mode 7 - gpio_115 4 i ae17 na safe_mode 7 - l l 7 vdda yes na pu/ pd lvcmos na g20 sdrc_a0 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na k20 sdrc_a1 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na j20 sdrc_a2 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na j21 sdrc_a3 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na u21 sdrc_a4 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na r20 sdrc_a5 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na m21 sdrc_a6 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na m20 sdrc_a7 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na n20 sdrc_a8 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na k21 sdrc_a9 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na y16 sdrc_a10 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na n21 sdrc_a11 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na r21 sdrc_a12 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na aa15 sdrc_a13 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na y12 sdrc_a14 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na aa18 sdrc_ba0 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na v20 sdrc_ba1 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na y15 sdrc_cke0 0 o h 1 7 vdds na 4 (1) pu/ pd lvcmos safe_mode_out1 (6) 7 na y13 sdrc_cke1 0 o h 1 7 vdds na 4 (1) pu/ pd lvcmos safe_mode_out1 (6) 7 na a12 sdrc_clk 0 io l 0 0 vdds yes 4 (1) pu/ pd lvcmos na d1 sdrc_d0 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na g1 sdrc_d1 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na g2 sdrc_d2 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na e1 sdrc_d3 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na d2 sdrc_d4 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na e2 sdrc_d5 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b3 sdrc_d6 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 45 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] na b4 sdrc_d7 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a10 sdrc_d8 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b11 sdrc_d9 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a11 sdrc_d10 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b12 sdrc_d11 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a16 sdrc_d12 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a17 sdrc_d13 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b17 sdrc_d14 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b18 sdrc_d15 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b7 sdrc_d16 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a5 sdrc_d17 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b6 sdrc_d18 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a6 sdrc_d19 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a8 sdrc_d20 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b9 sdrc_d21 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a9 sdrc_d22 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b10 sdrc_d23 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na c21 sdrc_d24 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na d20 sdrc_d25 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b19 sdrc_d26 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na c20 sdrc_d27 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na d21 sdrc_d28 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na e20 sdrc_d29 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na e21 sdrc_d30 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na g21 sdrc_d31 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na h1 sdrc_dm0 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na a14 sdrc_dm1 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na a4 sdrc_dm2 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na a18 sdrc_dm3 0 o 0 0 0 vdds na 4 (1) pu/ pd lvcmos na c2 sdrc_dqs0 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b15 sdrc_dqs1 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na b8 sdrc_dqs2 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na a19 sdrc_dqs3 0 io l z 0 vdds yes 4 (1) pu/ pd lvcmos na u20 sdrc_ncas 0 o 1 1 0 vdds na 4 (1) pu/ pd lvcmos na b13 sdrc_nclk 0 o 1 1 0 vdds na 4 (1) pu/ pd lvcmos na t21 sdrc_ncs0 0 o 1 1 0 vdds na 4 (1) pu/ pd lvcmos na t20 sdrc_ncs1 0 o 1 1 0 vdds na 4 (1) pu/ pd lvcmos na v21 sdrc_nras 0 o 1 1 0 vdds na 4 (1) pu/ pd lvcmos na y18 sdrc_nwe 0 o 1 1 0 vdds na 4 (1) pu/ pd lvcmos ae21 na dss_data0 0 io l l 7 vdda yes 8 pu/ pd lvcmos uart1_cts 2 i na gpio_70 4 io 8 safe_mode 7 - 8 ae22 na dss_data1 0 io l l 7 vdda yes 8 pu/ pd lvcmos uart1_rts 2 o 8 gpio_71 4 io 8 safe_mode 7 - 8 ae23 na dss_data2 0 io l l 7 vdda yes 8 pu/ pd lvcmos gpio_72 4 io 8 safe_mode 7 - 8 ae24 na dss_data3 0 io l l 7 vdda yes 8 pu/ pd lvcmos gpio_73 4 io 8 safe_mode 7 - 8 ad23 na dss_data4 0 io l l 7 vdda yes 8 pu/ pd lvcmos uart3_rx_irrx 2 i na 46 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] gpio_74 4 io 8 safe_mode 7 - 8 ad24 na dss_data5 0 io l l 7 vdda yes 8 pu/ pd lvcmos uart3_tx_irtx 2 o 8 gpio_75 4 io 8 safe_mode 7 - 8 ac26 na dss_data10 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_80 4 io safe_mode 7 - ad26 na dss_data11 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_81 4 io safe_mode 7 - aa25 na dss_data12 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_82 4 io safe_mode 7 - y25 na dss_data13 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_83 4 io safe_mode 7 - aa26 na dss_data14 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_84 4 io safe_mode 7 - ab26 na dss_data15 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_85 4 io safe_mode 7 - f25 na dss_data20 0 o h h 7 vdds yes 8 pu/ pd lvcmos mcspi3_somi 2 io dss_data2 3 io gpio_90 4 io safe_mode 7 - ac25 na dss_data22 0 o l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_cs1 2 o dss_data4 3 io gpio_92 4 io safe_mode 7 - ab25 na dss_data23 0 o l l 7 vdds yes 8 pu/ pd lvcmos dss_data5 3 io gpio_93 4 io safe_mode 7 - g25 na dss_pclk 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_66 4 io hw_dbg12 5 o safe_mode 7 - j2 na gpmc_a1 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_34 4 io safe_mode 7 - h1 na gpmc_a2 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_35 4 io safe_mode 7 - h2 na gpmc_a3 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_36 4 io safe_mode 7 - g2 na gpmc_a4 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_37 4 io safe_mode 7 - f1 na gpmc_a5 0 o l l 7 vdds yes 8 pu/ pd lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 47 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] gpio_38 4 io safe_mode 7 - f2 na gpmc_a6 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_39 4 io safe_mode 7 - e1 na gpmc_a7 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_40 4 io safe_mode 7 - e2 na gpmc_a8 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_41 4 io safe_mode 7 - d1 na gpmc_a9 0 o h h 7 vdds yes 8 pu/ pd lvcmos sys_ndmareq2 1 i gpio_42 4 io safe_mode 7 - d2 na gpmc_a10 0 o h h 7 vdds yes 8 pu/ pd lvcmos sys_ndmareq3 1 i gpio_43 4 io safe_mode 7 - n1 l1 gpmc_clk 0 o l 0 0 vdds yes 8 pu/ pd lvcmos gpio_59 4 io safe_mode 7 - aa2 u2 gpmc_d0 0 io h h 0 vdds yes 8 pu/ pd lvcmos aa1 u1 gpmc_d1 0 io h h 0 vdds yes 8 pu/ pd lvcmos ac2 v2 gpmc_d2 0 io h h 0 vdds yes 8 pu/ pd lvcmos ac1 v1 gpmc_d3 0 io h h 0 vdds yes 8 pu/ pd lvcmos ae5 aa3 gpmc_d4 0 io h h 0 vdds yes 8 pu/ pd lvcmos ad6 aa4 gpmc_d5 0 io h h 0 vdds yes 8 pu/ pd lvcmos ad5 y3 gpmc_d6 0 io h h 0 vdds yes 8 pu/ pd lvcmos ac5 y4 gpmc_d7 0 io h h 0 vdds yes 8 pu/ pd lvcmos v1 r1 gpmc_d8 0 io h h 0 vdds yes 8 pu/ pd lvcmos gpio_44 4 io safe_mode 7 - y1 t1 gpmc_d9 0 io h h 0 vdds yes 8 pu/ pd lvcmos gpio_45 4 io safe_mode 7 - t1 n1 gpmc_d10 0 io h h 0 vdds yes 8 pu/ pd lvcmos gpio_46 4 io safe_mode 7 - u2 p2 gpmc_d11 0 io h h 0 vdds yes 8 pu/ pd lvcmos gpio_47 4 io safe_mode 7 - u1 p1 gpmc_d12 0 io h h 0 vdds yes 8 pu/ pd lvcmos gpio_48 4 io safe_mode 7 - p1 m1 gpmc_d13 0 io h h 0 vdds yes 8 pu/ pd lvcmos gpio_49 4 io safe_mode 7 - l2 j2 gpmc_d14 0 io h h 0 vdds yes 8 pu/ pd lvcmos gpio_50 4 io safe_mode 7 - m2 k2 gpmc_d15 0 io h h 0 vdds yes 8 pu/ pd lvcmos gpio_51 4 io safe_mode 7 - ad10 aa9 gpmc_nadv_ale 0 o 0 0 0 vdds na 8 na lvcmos 48 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] k2 na gpmc_nbe0_cle 0 o l 0 0 vdds yes 8 pu/ pd lvcmos gpio_60 4 io safe_mode 7 - j1 na gpmc_nbe1 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_61 4 io safe_mode 7 - ad8 aa8 gpmc_ncs0 0 o 1 1 0 vdds na 8 na lvcmos ad1 w1 gpmc_ncs1 0 o h 1 0 vdds yes 8 pu/ pd lvcmos gpio_52 4 io safe_mode 7 - a3 na gpmc_ncs2 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_53 4 io safe_mode 7 - b6 na gpmc_ncs3 0 o h h 7 vdds yes 8 pu/ pd lvcmos sys_ndmareq0 1 i gpio_54 4 io safe_mode 7 - b4 na gpmc_ncs4 0 o h h 7 vdds yes 8 pu/ pd lvcmos sys_ndmareq1 1 i mcbsp4_clkx 2 io gpt_9_pwm_evt 3 io gpio_55 4 io safe_mode 7 - c4 na gpmc_ncs5 0 o h h 7 vdds yes 8 pu/ pd lvcmos sys_ndmareq2 1 i mcbsp4_dr 2 i gpt_10_pwm_evt 3 io gpio_56 4 io safe_mode 7 - b5 na gpmc_ncs6 0 o h h 7 vdds yes 8 pu/ pd lvcmos sys_ndmareq3 1 i mcbsp4_dx 2 io gpt_11_pwm_evt 3 io gpio_57 4 io safe_mode 7 - c5 na gpmc_ncs7 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpmc_io_dir 1 o mcbsp4_fsx 2 io gpt_8_pwm_evt 3 io gpio_58 4 io safe_mode 7 - n2 l2 gpmc_noe 0 o 1 1 0 vdds na 8 na lvcmos m1 k1 gpmc_nwe 0 o 1 1 0 vdds na 8 na lvcmos ac6 y5 gpmc_nwp 0 o l 0 0 vdds yes 8 pu/ pd lvcmos gpio_62 4 io safe_mode 7 - ac11 y10 gpmc_wait0 0 i h h 0 vdds yes na pu/ pd lvcmos ac8 y8 gpmc_wait1 0 i h h 7 vdds yes 8 pu/ pd lvcmos gpio_63 4 io safe_mode 7 - b3 na gpmc_wait2 0 i h h 7 vdds yes 8 pu/ pd lvcmos uart4_tx 2 o gpio_64 4 io safe_mode 7 - c6 na gpmc_wait3 0 i h h 7 vdds yes 8 pu/ pd lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 49 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] sys_ndmareq1 1 i uart4_rx 2 i gpio_65 4 io safe_mode 7 - w19 na hsusb0_clk 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_120 4 io safe_mode 7 - v20 na hsusb0_data0 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_tx_irtx 2 o gpio_125 4 io uart2_tx 5 o safe_mode 7 - y20 na hsusb0_data1 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rx_irrx 2 i gpio_130 4 io uart2_rx 5 i safe_mode 7 - v18 na hsusb0_data2 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rts_sd 2 o gpio_131 4 io uart2_rts 5 o safe_mode 7 - w20 na hsusb0_data3 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_cts_rctx 2 io gpio_169 4 io uart2_cts 5 i safe_mode 7 - w17 na hsusb0_data4 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_188 4 io safe_mode 7 - y18 na hsusb0_data5 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_189 4 io safe_mode 7 - y19 na hsusb0_data6 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_190 4 io safe_mode 7 - y17 na hsusb0_data7 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_191 4 io safe_mode 7 - v19 na hsusb0_dir 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_122 4 io safe_mode 7 - w18 na hsusb0_nxt 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_124 4 io safe_mode 7 - u20 na hsusb0_stp 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_121 4 io safe_mode 7 - u15 na jtag_ntrst 0 i l l 0 vdds yes na pu/ pd lvcmos w13 na jtag_rtck 0 o l 0 0 vdds na 4 pu/ pd lvcmos v14 na jtag_tck 0 i l l 0 vdds yes na pu/ pd lvcmos u16 na jtag_tdi 0 i h h 0 vdds yes na pu/ pd lvcmos y13 na jtag_tdo 0 o l z 0 vdds na 4 pu/ pd lvcmos v15 na jtag_tms_tmsc 0 io h h 0 vdds yes 4 pu/ pd lvcmos 50 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] n19 na mmc1_clk 0 o l l 7 vdds_mmc1 ( yes 1 pu/ pd (3) lvcmos 13) gpio_120 (8) 4 io safe_mode 7 - l18 na mmc1_cmd 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (3) lvcmos 13) gpio_121 (8) 4 io safe_mode 7 - m19 na mmc1_dat0 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (3) lvcmos 13) gpio_122 (8) 4 io safe_mode 7 - m18 na mmc1_dat1 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (3) lvcmos 13) gpio_123 (8) 4 io safe_mode 7 - k18 na mmc1_dat2 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (3) lvcmos 13) gpio_124 (8) 4 io safe_mode 7 - n20 na mmc1_dat3 0 io l l 7 vdds_mmc1 ( yes 1 pu/ pd (3) lvcmos 13) gpio_125 (8) 4 io safe_mode 7 - m20 na gpio_126 (8) 4 io l l 7 vdds_ x yes 1 pu/pd (3) lvcmos safe_mode 7 - p17 na gpio_127 (8) 4 io l l 7 vdds_ x yes 1 pu/pd (3) lvcmos safe_mode 7 - p18 na gpio_128 4 io l l 7 vdds yes 4 pu/pd lvcmos safe_mode 7 - p19 na gpio_129 (8) 4 io l l 7 vdds_ x yes 1 pu/pd (3) lvcmos safe_mode 7 - j25 na i2c1_scl 0 od h h 0 vdds na 3 pu/ pd (9) (10) open drain j24 na i2c1_sda 0 iod h h 0 vdds yes 3 pu/ pd (9) (10) lvcmos open drain c2 na i2c2_scl 0 od h h 7 vdds yes 3 pu/ pd (9) (11) lvcmos open drain gpio_168 4 io 4 safe_mode 7 - 4 c1 na i2c2_sda 0 iod h h 7 vdds yes 3 pu/ pd (9) (11) lvcmos open drain gpio_183 4 io 4 safe_mode 7 - 4 ab4 na i2c3_scl 0 od h h 7 vdds yes 3 pu/ pd (9) (11) lvcmos open drain gpio_184 4 io 4 safe_mode 7 - 4 ac4 na i2c3_sda 0 iod h h 7 vdds yes 3 pu/ pd (9) (11) lvcmos open drain gpio_185 4 io 4 safe_mode 7 - 4 u19 na mcbsp1_clkr 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_clk 1 io gpio_156 4 io safe_mode 7 - t17 na mcbsp1_clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcbsp3_clkx 2 io gpio_162 4 io safe_mode 7 - copyright ? 2010 C 2011, texas instruments incorporated terminal description 51 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] t20 na mcbsp1_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_somi 1 io mcbsp3_dr 2 i gpio_159 4 io safe_mode 7 - u17 na mcbsp1_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_simo 1 io mcbsp3_dx 2 io gpio_158 4 io safe_mode 7 - v17 na mcbsp1_fsr 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io gpio_157 4 io safe_mode 7 - p20 na mcbsp1_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_cs0 1 io mcbsp3_fsx 2 io gpio_161 4 io safe_mode 7 - r18 na mcbsp2_clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_117 4 io safe_mode 7 - t18 na mcbsp2_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_118 4 io safe_mode 7 - r19 na mcbsp2_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_119 4 io safe_mode 7 - u18 na mcbsp2_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_116 4 io safe_mode 7 - p9 na mcspi1_clk 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat4 1 io gpio_171 4 io safe_mode 7 - r7 na mcspi1_cs0 0 io h h 7 vdds yes 4 pu/ pd lvcmos mmc2_dat7 1 io gpio_174 4 io safe_mode 7 - r9 na mcspi1_cs2 0 o h h 7 vdds yes 4 pu/ pd lvcmos mmc3_clk 3 o gpio_176 4 io safe_mode 7 - p8 na mcspi1_simo 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat5 1 io gpio_172 4 io safe_mode 7 - p7 na mcspi1_somi 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat6 1 io gpio_173 4 io safe_mode 7 - w7 na mcspi2_clk 0 io l l 7 vdds yes 4 pu/ pd lvcmos hsusb2_data7 3 io gpio_178 4 io safe_mode 7 - 52 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] v8 na mcspi2_cs0 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpt_11_pwm_evt 1 io hsusb2_data6 3 io gpio_181 4 io safe_mode 7 - w8 na mcspi2_simo 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt_9_pwm_evt 1 io hsusb2_data4 3 io gpio_179 4 io safe_mode 7 - u8 na mcspi2_somi 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt_10_pwm_evt 1 io hsusb2_data5 3 io gpio_180 4 io safe_mode 7 - w10 na mmc2_clk 0 o l l 7 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io gpio_130 4 io safe_mode 7 - r10 na mmc2_cmd 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_simo 1 io gpio_131 4 io safe_mode 7 - t10 na mmc2_dat0 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_somi 1 io gpio_132 4 io safe_mode 7 - t9 na mmc2_dat1 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_133 4 io safe_mode 7 - u10 na mmc2_dat2 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o gpio_134 4 io safe_mode 7 - u9 na mmc2_dat3 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io gpio_135 4 io safe_mode 7 - v10 na mmc2_dat4 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat0 1 o mmc3_dat0 3 io gpio_136 4 io safe_mode 7 - r2 na uart1_rts 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_149 4 io safe_mode 7 - h3 na uart1_rx 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcbsp1_clkr 2 io mcspi4_clk 3 io gpio_151 4 io safe_mode 7 - l4 na uart1_tx 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_148 4 io safe_mode 7 - y24 na uart2_cts 0 i h h 7 vdds yes 4 pu/ pd lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 53 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] mcbsp3_dx 1 io gpt_9_pwm_evt 2 io gpio_144 4 io safe_mode 7 - aa24 na uart2_rts 0 o h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_dr 1 i gpt_10_pwm_evt 2 io gpio_145 4 io safe_mode 7 - ad21 na uart2_rx 0 i h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_fsx 1 io gpt_8_pwm_evt 2 io gpio_147 4 io safe_mode 7 - ad22 na uart2_tx 0 o h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_clkx 1 io gpt_11_pwm_evt 2 io gpio_146 4 io safe_mode 7 - f23 na uart3_cts_rctx 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_163 4 io safe_mode 7 - f24 na uart3_rts_sd 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_164 4 io safe_mode 7 - h24 na uart3_rx_irrx 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_165 4 io safe_mode 7 - g24 na uart3_tx_irtx 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_166 4 io safe_mode 7 - j23 na hdq_sio 0 iod h h 7 vdds yes 4 pu/ pd lvcmos open drain sys_altclk 1 i i2c2_sccbe 2 od i2c3_sccbe 3 od gpio_170 4 io safe_mode 7 - ad15 na i2c4_scl 0 od h h 0 vdds yes 3 pu/ pd (9) (10) lvcmos open drain sys_nvmode1 1 o 4 safe_mode 7 - 4 w16 na i2c4_sda 0 iod h h 0 vdds yes 3 pu/ pd (9) (10) lvcmos open drain sys_nvmode2 1 o 4 safe_mode 7 - 4 f3 na sys_boot0 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data18 3 io gpio_2 4 io safe_mode 7 - d3 na sys_boot1 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data19 3 io gpio_3 4 io safe_mode 7 - c3 na sys_boot2 0 i z z 0 vdds yes 8 pu/ pd lvcmos gpio_4 4 io 54 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] safe_mode 7 - e3 na sys_boot3 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data20 3 o gpio_5 4 io safe_mode 7 - e4 na sys_boot4 0 i z z 0 vdds yes 8 pu/ pd lvcmos mmc2_dir_dat2 1 o dss_data21 3 o gpio_6 4 io safe_mode 7 - g3 na sys_boot5 0 i z z 0 vdds yes 8 pu/ pd lvcmos mmc2_dir_dat3 1 o dss_data22 3 o gpio_7 4 io safe_mode 7 - d4 na sys_boot6 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data23 3 o gpio_8 4 io safe_mode 7 - ae14 na sys_clkout1 0 o l l 7 (12) vdds yes 4 pu/ pd lvcmos gpio_10 4 io safe_mode 7 - w11 na sys_clkout2 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_186 4 io safe_mode 7 - w15 na sys_clkreq 0 io 0 see (7) 0 vdds yes 4 pu/ pd lvcmos gpio_1 4 io safe_mode 7 - v16 na sys_nirq 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_0 4 io safe_mode 7 - v13 na sys_nrespwron 0 i z z 0 vdds yes na no lvcmos ad7 aa5 sys_nreswarm 0 iod 0 h 0 vdds yes 4 pu/ pd lvcmos gpio_30 4 io open drain safe_mode 7 - v12 na sys_off_mode 0 o 0 l 7 vdds yes 4 pu/ pd lvcmos gpio_9 4 io safe_mode 7 - af19 na sys_xtalin 0 ai z z 0 vdds yes na na lvcmos analog af20 na sys_xtalout 0 ao z 0 0 vdds na na na analog w26 na cvideo1_out 0 ao 0 0 0 vdda_dac na na na 10-bit dac v26 na cvideo2_out 0 ao 0 0 0 vdda_dac na na na 10-bit dac w25 na cvideo1_vfb 0 ao 0 na 0 vdda_dac na na na 10-bit dac u24 na cvideo2_vfb 0 ao 0 na 0 vdda_dac na na na 10-bit dac v23 na cvideo1_rset 0 aio z na 0 vdda_dac no na na 10-bit dac ae20 na sys_32k 0 i z z 0 vdds yes na pu/ pd lvcmos a24 na cam_d2 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_101 4 io hw_dbg4 5 o safe_mode 7 - b24 na cam_d3 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_102 4 io hw_dbg5 5 o safe_mode 7 - copyright ? 2010 C 2011, texas instruments incorporated terminal description 55 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] d24 na cam_d4 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_103 4 io hw_dbg6 5 o safe_mode 7 - c24 na cam_d5 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_104 4 io hw_dbg7 5 o safe_mode 7 - d25 na cam_d10 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_109 4 io hw_dbg8 5 o safe_mode 7 - e26 na cam_d11 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_110 4 io hw_dbg9 5 o safe_mode 7 - b23 na cam_fld 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io gpio_98 4 io hw_dbg3 5 o safe_mode 7 - c23 na cam_hs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_94 4 io hw_dbg0 5 o safe_mode 7 - c26 na cam_pclk 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_97 4 io hw_dbg2 5 o safe_mode 7 - d26 na cam_strobe 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_126 4 io hw_dbg11 5 o safe_mode 7 - c25 na cam_xclka 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_96 4 io safe_mode 7 - e25 na cam_xclkb 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_111 4 io safe_mode 7 - p25 na cam_d6 0 i l l 7 vdd s yes na pu/ pd sublvds gpio_105 4 i safe_mode 7 - p26 na cam_d7 0 i l l 7 vdd s yes na pu/ pd sublvds gpio_106 4 i safe_mode 7 - n25 na cam_d8 0 i l l 7 vdd s na na pu/ pd sublvds gpio_107 4 i safe_mode 7 - n26 na cam_d9 0 i l l 7 vdd s na na pu/ pd sublvds gpio_108 4 i safe_mode 7 - d23 na cam_vs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_95 4 io hw_dbg1 5 o safe_mode 7 - 56 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] a23 na cam_wen 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_shutter 2 o gpio_167 4 io hw_dbg10 5 o safe_mode 7 - f26 na dss_acbias 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_69 4 io safe_mode 7 - g26 na dss_data6 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_tx 2 o gpio_76 4 io hw_dbg14 5 o safe_mode 7 - h25 na dss_data7 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_rx 2 i gpio_77 4 io hw_dbg15 5 o safe_mode 7 - h26 na dss_data8 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart3_rx_irrx 2 i gpio_78 4 io hw_dbg16 5 o safe_mode 7 - j26 na dss_data9 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart3_tx_irtx 2 o gpio_79 4 io hw_dbg17 5 o safe_mode 7 - l25 na dss_data16 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_86 4 io safe_mode 7 - l26 na dss_data17 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_87 4 io safe_mode 7 - m24 na dss_data18 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_clk 2 io dss_data0 3 io gpio_88 4 io safe_mode 7 - m26 na dss_data19 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_simo 2 io dss_data1 3 io gpio_89 4 io safe_mode 7 - n24 na dss_data21 0 o l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_cs0 2 io dss_data3 3 io gpio_91 4 io safe_mode 7 - k24 na dss_hsync 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_67 4 io hw_dbg13 5 o safe_mode 7 - m25 na dss_vsync 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_68 4 io copyright ? 2010 C 2011, texas instruments incorporated terminal description 57 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] safe_mode 7 - r8 na mcspi1_cs1 0 o h h 7 vdds yes 4 pu/ pd lvcmos mmc3_cmd 3 io gpio_175 4 io safe_mode 7 - t8 na mcspi1_cs3 0 o h h 7 vdds yes 4 pu/ pd lvcmos hsusb2_data2 3 io gpio_177 4 io mm2_txdat 5 io safe_mode 7 - v9 na mcspi2_cs1 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpt_8_pwm_evt 1 io hsusb2_data3 3 io gpio_182 4 io mm2_txen_n 5 io safe_mode 7 - t19 na mcbsp_clks 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_shutter 2 o gpio_160 4 io uart1_cts 5 i safe_mode 7 - ab2 na etk_clk 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcbsp5_clkx 1 io mmc3_clk 2 o hsusb1_stp 3 o gpio_12 4 io mm1_rxdp 5 io hw_dbg0 7 o ab3 na etk_ctl 0 o h h 4 vdds yes 4 pu/ pd lvcmos mmc3_cmd 2 io hsusb1_clk 3 o gpio_13 4 io hw_dbg1 7 o ac3 na etk_d0 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_simo 1 io mmc3_dat4 2 io hsusb1_data0 3 io gpio_14 4 io mm1_rxrcv 5 io hw_dbg2 7 o ad4 na etk_d1 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_somi 1 io hsusb1_data1 3 io gpio_15 4 io mm1_txse0 5 io hw_dbg3 7 o ad3 na etk_d2 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io hsusb1_data2 3 io gpio_16 4 io mm1_txdat 5 io hw_dbg4 7 o aa3 na etk_d3 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io mmc3_dat3 2 io 58 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] hsusb1_data7 3 io gpio_17 4 io hw_dbg5 7 o y3 na etk_d4 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dr 1 i mmc3_dat0 2 io hsusb1_data4 3 io gpio_18 4 io hw_dbg6 7 o ab1 na etk_d5 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_fsx 1 io mmc3_dat1 2 io hsusb1_data5 3 io gpio_19 4 io hw_dbg7 7 o ae3 na etk_d6 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dx 1 o mmc3_dat2 2 io hsusb1_data6 3 io gpio_20 4 io hw_dbg8 7 o ad2 na etk_d7 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o mmc3_dat7 2 io hsusb1_data3 3 io gpio_21 4 io mm1_txen_n 5 io hw_dbg9 7 o aa4 na etk_d8 0 o l l 4 vdds yes 4 pu/ pd lvcmos mmc3_dat6 2 io hsusb1_dir 3 i gpio_22 4 io hw_dbg10 7 o v2 na etk_d9 0 o l l 4 vdds yes 4 pu/ pd lvcmos mmc3_dat5 2 io hsusb1_nxt 3 i gpio_23 4 io mm1_rxdm 5 io hw_dbg11 7 o ae4 na etk_d10 0 o l l 4 vdds yes 4 pu/ pd lvcmos uart1_rx 2 i hsusb2_clk 3 o gpio_24 4 io hw_dbg12 7 o af6 na etk_d11 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_stp 3 o gpio_25 4 io mm2_rxdp 5 io hw_dbg13 7 o ae6 na etk_d12 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_dir 3 i gpio_26 4 io hw_dbg14 7 o af7 na etk_d13 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_nxt 3 i copyright ? 2010 C 2011, texas instruments incorporated terminal description 59 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] gpio_27 4 io mm2_rxdm 5 io hw_dbg15 7 o af9 na etk_d14 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_data0 3 io gpio_28 4 io mm2_rxrcv 5 io hw_dbg16 7 o ae9 na etk_d15 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_data1 3 io gpio_29 4 io mm2_txse0 5 io hw_dbg17 7 o y15 na jtag_emu0 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_11 4 io safe_mode 7 - y14 na jtag_emu1 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_31 4 io safe_mode 7 - u3 na mcbsp3_clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_tx 1 o gpio_142 4 io safe_mode 7 - n3 na mcbsp3_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos uart2_rts 1 o gpio_141 4 io safe_mode 7 - p3 na mcbsp3_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_cts 1 i gpio_140 4 io safe_mode 7 - w3 na mcbsp3_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_rx 1 i gpio_143 4 io safe_mode 7 - v3 na mcbsp4_clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_152 4 io mm3_txse0 6 io safe_mode 7 - u4 na mcbsp4_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_153 4 io mm3_rxrcv 6 io safe_mode 7 - r3 na mcbsp4_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_154 4 io mm3_txdat 6 io safe_mode 7 - t3 na mcbsp4_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_155 4 io mm3_txen_n 6 io safe_mode 7 - m3 na mmc2_dat5 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat1 1 o cam_global_reset 2 io mmc3_dat1 3 io 60 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] gpio_137 4 io mm3_rxdp 6 io safe_mode 7 - l3 na mmc2_dat6 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_cmd 1 o cam_shutter 2 o mmc3_dat2 3 io gpio_138 4 io safe_mode 7 - k3 na mmc2_dat7 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_clkin 1 i mmc3_dat3 3 io gpio_139 4 io mm3_rxdm 6 io safe_mode 7 - w2 na uart1_cts 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_150 4 io safe_mode 7 - ac16 na vss 0 gnd ad18 na vdd s 0 pwr l19 na vss 0 gnd ac19 na vss 0 gnd ad19 na vdd s 0 pwr l20 na vdd s 0 pwr p23 na vdds _x 0 pwr ae19 na cap_vddu_array 0 pwr ac21, d15, na vdd_core 0 pwr - - - - - - - - g11, g18, h20, m7, m17, r20, t7, y8, y12 d13, g9, na vdd_mpu_iva 0 pwr - - - - - - - - g12, h7, k11, l9, m9, m10, n7, n8, p10, u7, u11, u13, v7, v11, w9, y9, y11 a18, ac7, a3, a15, b5, vdds 0 pwr - - - - - - - - ac15, f2, f21, ac18, l20, w21 ac24, ad20, ae10, c11, d9, e24, g4, j15, j18, l7, l24, m4, t4, t24, w24, y4, ab24 u12 na vdds_sram 0 pwr - - - - - - - - k13 na vdda_dplls_dll 0 pwr - - - - - - - - u14 na vdda_dpll_per 0 pwr - - - - - - - - w14 na vdda_wkup_bg_bb 0 pwr - - - - - - - - n23 na vdds_mmc1 0 pwr - - - - - - - - v25 na vdda_dac 0 pwr - - - - - - - - v24 na vssa_dac 0 gnd - - - - - - - - copyright ? 2010 C 2011, texas instruments incorporated terminal description 61 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] a6, a8, a13, a7, a13, vss 0 gnd - - - - - - - - ab5, ab22, b14, c1, f1, ac10, f20, h2, ad14, h20, l21, ad25, ae7, m2, p20, b2, b25, r2, w20 y6, c12, d7, y11, aa7, d10, d12, aa16 d14, d18, d20, e22, g1, g8, g10, g20, g23, h4, k1, k15, k25, l10, l17, l23, n4, n10, n17, r1, r4, r17, t23, u25, w1, w4, w23, y7, y10, y16, y26 k14 na cap_vddu_wkup_log 0 pwr - - - - - - - - ic a1, l1, t2, a1, j1, n2, feed-through - - - - - - - - - - y2, ae2, t2, w2, y2, pins (4) af4, af5, aa6, y7, af8, af10, y9, aa10, af12, af13, aa11, af14, af15, aa12, af17, af16, aa13, y14, a20, af21, aa14, b16, af18, af24, y17, aa17, af22, a25, y19, aa19, ae25, af25, a20, y20, a26, b26, aa20, a21, k26, u26, b21, h21, ae26, af26 p21, y21, aa21 62 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-2. ball characteristics (cbc pkg.) (5) (continued) ball ball top pin name [2] mode [3] type [4] ball ball reset reset power [8] hys [9] buffer pullup io cell bottom [1] reset rel. state rel. mode strength /down [12] [1] state [5] [6] [7] (ma) [10] type [11] a2, af1, a2, aa1, no connect (2) - - - - - - - - - - b1,d5, k23, aa2,b1, b2, a5, a7, a9, b20, y1 a10, a11, a12, a14, a15, a16, a17, a19, a21, a22, aa23, ab23, ac9, ac12, ac13, ac14, ac17, ac20, ac22, ac23, ad9, ad11, ad12, ad13, ae1, ae8, ae11, ae12, ae13, af2, af3, af11, b7, b8, b9, b10, b11, b12, b13, b14, b15, b16, b17, b18, b19, b20, b21, b22, c7, c8, c9, c10, c13, c14, c15, c16, c17 c18, c19, c20, c21, c22, d8, d11, d16, d17, d19, d21, d22, e23, f4, g7, g13, g14, g15, g16, g17, g19, h8, h9, h10, h11, h12, h13, h14, h15, h16, h17, h18, h19, h23, j3, j4, j7, j8, j9, j10, j11, j12, j13, j14, j16, j17, j19, j20, k4, k7, k8, k9, k10, k12, k16, k17, k19, l8, m8, m23, n18, p2, p4, p24, r23, r24, r25, r26, t25, t26, u23, v4, w12, y23 af23 na sys_xtalgnd 0 gnd a4 na gpmc_a11 0 o l l 7 vdds yes 8 pu/pd lvcmos safe_mode 7 d6 na cap_vdd_bb_mpu_i 0 pwr va n9 na cap_vdd_sram_mpu 0 pwr _iva k20 na cap_vdd_sram_core 0 pwr copyright ? 2010 C 2011, texas instruments incorporated terminal description 63 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) the drive strength of these ios is set according to the programmable load range: 2 pf to 4 pf per default or 4 pf to 12 pf. for a full description of the drive strength programming, see the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (2) pins labeled as "no connect" must be left unconnected. any connections to these pins may result in unpredictable behavior. (3) pu = [50 to 100 k ] per default or [10 to 50 k ] according to the selected mode. for a full description of the pull-up drive strength programming, see the prg_sdmmc_pustrength configuration register bit field in the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). pd: 30 to 150 k . (4) these signals are feed-through balls. for more information, see table 2-27 . (5) na in this table stands for "not applicable". (6) in the safe_mode_out1, the buffer is configured to drive 1. (7) depending on the sys_clkreq direction the corresponding reset released state value can be: C z if sys_clkreq is used as input C 1 if sys_clkreq is used as output for a full description of the sys_clkreq control, see power, reset, and clock management chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (8) the usage of this gpio is strongly restricted. for more information, see the general-purpose interface chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (9) the pullup and pulldown can be either the standard lvcmos 100- a drive strength or the i2c pullup and pulldown described as follows: nominal resistance = 1.66 k in high-speed mode with a load range of 5 pf to 12 pf, 4.5 k in standard / fast mode with a load range of 5 pf to 15 pf. (10) the default buffer configuration is high-speed i2c point-to-point mode using internal pullup. for a full description of the pull drive strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the control_prog_io1, control_prog_io_wkup1 control modules in the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) to modify the io settings if required by the targeted interface application. (11) the default buffer configuration is standard lvcmos mode (non-i2c). for a full description of the pull drive strength programming, see padconfs bits of control_padconf_x control modules (standard lvcmos mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the control_prog_io2, control_prog_io3 control modules (i2c mode) in the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) to modify the io settings if required by the targeted interface application. (12) mux0 if sys_boot6 is pulled down (clock master). (13) if mmc1 functional signals are enabled, vdds_mmc1 for mmc1 must be supplied by a dedicated power source. if mmc1 functional signals are disabled, other multiplexed cmos signals of the interface can be enabled. the interface can be supplied by the same power source as vdds. the vdds power source supplies the vdds_mmc1 ball. if neither mmc1 functional balls or cmos signals are enabled, the interface balls are left unconnected with its associated power supply (vdda/vssa) grounded. for the corresponding setting of the pbiaslitepwrdnz0 bit, see the system control module / scm programming model / extended-drain i/os and pbias cells programming guide section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-3. ball characteristics (cus pkg.) (1) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] d7 sdrc_d0 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c5 sdrc_d1 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c6 sdrc_d2 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b5 sdrc_d3 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos d9 sdrc_d4 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos d10 sdrc_d5 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c7 sdrc_d6 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b7 sdrc_d7 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b11 sdrc_d8 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c12 sdrc_d9 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b12 sdrc_d10 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos d13 sdrc_d11 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c13 sdrc_d12 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b14 sdrc_d13 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos a14 sdrc_d14 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b15 sdrc_d15 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c9 sdrc_d16 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos 64 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] e12 sdrc_d17 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b8 sdrc_d18 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b9 sdrc_d19 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c10 sdrc_d20 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b10 sdrc_d21 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos d12 sdrc_d22 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos e13 sdrc_d23 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos e15 sdrc_d24 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos d15 sdrc_d25 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c15 sdrc_d26 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b16 sdrc_d27 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c16 sdrc_d28 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos d16 sdrc_d29 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b17 sdrc_d30 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos b18 sdrc_d31 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos c18 sdrc_ba0 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos d18 sdrc_ba1 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos a4 sdrc_a0 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos b4 sdrc_a1 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos d6 sdrc_a2 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos b3 sdrc_a3 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos b2 sdrc_a4 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos c3 sdrc_a5 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos e3 sdrc_a6 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos f6 sdrc_a7 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos e10 sdrc_a8 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos e9 sdrc_a9 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos e7 sdrc_a10 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos g6 sdrc_a11 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos g7 sdrc_a12 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos f7 sdrc_a13 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos f9 sdrc_a14 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos a19 sdrc_ncs0 0 o 1 1 0 vdds_mem na 4 (8) pu/ pd lvcmos b19 sdrc_ncs1 0 o 1 1 0 vdds_mem na 4 (8) pu/ pd lvcmos a10 sdrc_clk 0 io l 0 0 vdds_mem yes 4 (8) pu/ pd lvcmos a11 sdrc_nclk 0 o 1 1 0 vdds_mem na 4 (8) pu/ pd lvcmos b20 sdrc_cke0 0 o h 1 7 vdds_mem na 4 (8) pu/ pd lvcmos safe_mode_out1 (9) 7 c20 sdrc_cke1 0 o h 1 7 vdds_mem na 4 (8) pu/ pd lvcmos safe_mode_out1 (9) 7 d19 sdrc_nras 0 o 1 1 0 vdds_mem na 4 (8) pu/ pd lvcmos c19 sdrc_ncas 0 o 1 1 0 vdds_mem na 4 (8) pu/ pd lvcmos a20 sdrc_nwe 0 o 1 1 0 vdds_mem na 4 (8) pu/ pd lvcmos b6 sdrc_dm0 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos b13 sdrc_dm1 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos a7 sdrc_dm2 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos a16 sdrc_dm3 0 o 0 0 0 vdds_mem na 4 (8) pu/ pd lvcmos a5 sdrc_dqs0 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos a13 sdrc_dqs1 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos a8 sdrc_dqs2 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos a17 sdrc_dqs3 0 io l z 0 vdds_mem yes 4 (8) pu/ pd lvcmos k4 gpmc_a1 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_34 4 io safe_mode 7 k3 gpmc_a2 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos copyright ? 2010 C 2011, texas instruments incorporated terminal description 65 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] gpio_35 4 io safe_mode 7 k2 gpmc_a3 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_36 4 io safe_mode 7 j4 gpmc_a4 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_37 4 io safe_mode 7 j3 gpmc_a5 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_38 4 io safe_mode 7 j2 gpmc_a6 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpio_39 4 io safe_mode 7 j1 gpmc_a7 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpio_40 4 io safe_mode 7 h1 gpmc_a8 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpio_41 4 io safe_mode 7 h2 gpmc_a9 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq2 1 i gpio_42 4 io safe_mode 7 g2 gpmc_a10 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq3 1 i gpio_43 4 io safe_mode 7 l2 gpmc_d0 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos m1 gpmc_d1 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos m2 gpmc_d2 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos n2 gpmc_d3 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos m3 gpmc_d4 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos p1 gpmc_d5 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos p2 gpmc_d6 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos r1 gpmc_d7 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos r2 gpmc_d8 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_44 4 io safe_mode 7 t2 gpmc_d9 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_45 4 io safe_mode 7 u1 gpmc_d10 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_46 4 io safe_mode 7 r3 gpmc_d11 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_47 4 io safe_mode 7 t3 gpmc_d12 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_48 4 io safe_mode 7 u2 gpmc_d13 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_49 4 io safe_mode 7 v1 gpmc_d14 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos 66 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] gpio_50 4 io safe_mode 7 v2 gpmc_d15 0 io h h 0 vdds_mem yes 8 pu/ pd lvcmos gpio_51 4 io safe_mode 7 e2 gpmc_ncs0 0 o 1 1 0 vdds_mem na 8 na lvcmos d2 gpmc_ncs3 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq0 1 i gpio_54 4 io safe_mode 7 f4 gpmc_ncs4 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq1 1 i mcbsp4_ clkx 2 io gpt_9_pwm_evt 3 io gpio_55 4 io safe_mode 7 g5 gpmc_ncs5 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq2 1 i mcbsp4_dr 2 i gpt_10_pwm_evt 3 io gpio_56 4 io safe_mode 7 f3 gpmc_ncs6 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq3 1 i mcbsp4_dx 2 io gpt_11_pwm_evt 3 io gpio_57 4 io safe_mode 7 g4 gpmc_ncs7 0 o h h 7 vdds_mem yes 8 pu/ pd lvcmos gpmc_io_dir 1 o mcbsp4_fsx 2 io gpt_8_pwm_evt 3 io gpio_58 4 io safe_mode 7 w2 gpmc_clk 0 o l 0 0 vdds_mem yes 8 pu/ pd lvcmos gpio_59 4 io safe_mode 7 f1 gpmc_nadv_ale 0 o 0 0 0 vdds_mem na 8 pu/ pd lvcmos f2 gpmc_noe 0 o 1 1 0 vdds_mem na 8 pu/ pd lvcmos g3 gpmc_nwe 0 o 1 1 0 vdds_mem na 8 pu/ pd lvcmos k5 gpmc_nbe0_cle 0 o l 0 0 vdds_mem yes 8 pu/ pd lvcmos gpio_60 4 io safe_mode 7 l1 gpmc_nbe1 0 o l l 7 vdds_mem yes 8 pu/ pd lvcmos gpio_61 4 io safe_mode 7 e1 gpmc_nwp 0 o l 0 0 vdds_mem yes 8 pu/ pd lvcmos gpio_62 4 io safe_mode 7 c1 gpmc_wait0 0 i h h 0 vdds_mem yes na pu/ pd lvcmos c2 gpmc_wait3 0 i h h 7 vdds_mem yes 8 pu/ pd lvcmos sys_ndmareq1 1 i uart4_rx 2 i gpio_65 4 io safe_mode 7 copyright ? 2010 C 2011, texas instruments incorporated terminal description 67 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] g22 dss_pclk 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_66 4 io hw_dbg12 5 o safe_mode 7 e22 dss_hsync 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_67 4 io hw_dbg13 5 o safe_mode 7 f22 dss_vsync 0 o h h 7 vdds yes 8 pu/ pd lvcmos gpio_68 4 io safe_mode 7 j21 dss_acbias 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_69 4 io safe_mode 7 ac19 dss_data0 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_cts 2 i na gpio_70 4 io 8 safe_mode 7 8 ab19 dss_data1 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_rts 2 o 8 gpio_71 4 io 8 safe_mode 7 8 ad20 dss_data2 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_72 4 io 8 safe_mode 7 8 ac20 dss_data3 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_73 4 io 8 safe_mode 7 8 ad21 dss_data4 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart3_rx_ irrx 2 i na gpio_74 4 io 8 safe_mode 7 8 ac21 dss_data5 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart3_tx_ irtx 2 o 8 gpio_75 4 io 8 safe_mode 7 8 d24 dss_data6 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_tx 2 o gpio_76 4 io hw_dbg14 5 o safe_mode 7 e23 dss_data7 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_rx 2 i gpio_77 4 io hw_dbg15 5 o safe_mode 7 e24 dss_data8 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart3_rx_irrx 2 i gpio_78 4 io hw_dbg16 5 o safe_mode 7 f23 dss_data9 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart3_tx_irtx 2 o gpio_79 4 io hw_dbg17 5 o 68 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] safe_mode 7 ac22 dss_data10 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_80 4 io safe_mode 7 ac23 dss_data11 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_81 4 io safe_mode 7 ab22 dss_data12 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_82 4 io safe_mode 7 y22 dss_data13 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_83 4 io safe_mode 7 w22 dss_data14 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_84 4 io safe_mode 7 v22 dss_data15 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_85 4 io safe_mode 7 j22 dss_data16 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_86 4 io safe_mode 7 g23 dss_data17 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_87 4 io safe_mode 7 g24 dss_data18 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_clk 2 io dss_data0 3 io gpio_88 4 io safe_mode 7 h23 dss_data19 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_simo 2 io dss_data1 3 io gpio_89 4 io safe_mode 7 d23 dss_data20 0 o h h 7 vdds yes 8 pu/ pd lvcmos mcspi3_somi 2 io dss_data2 3 io gpio_90 4 io safe_mode 7 k22 dss_data21 0 o l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_cs0 2 io dss_data3 3 io gpio_91 4 io safe_mode 7 v21 dss_data22 0 o l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_cs1 2 o dss_data4 3 io gpio_92 4 io safe_mode 7 w21 dss_data23 0 o l l 7 vdds yes 8 pu/ pd lvcmos dss_data5 3 io gpio_93 4 io safe_mode 7 aa23 cvideo2_out 0 ao 0 0 0 vdda_dac na na (6) na 10-bit dac copyright ? 2010 C 2011, texas instruments incorporated terminal description 69 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] ab24 cvideo1_out 0 ao 0 0 0 vdda_dac na na (6) na 10-bit dac ab23 cvideo1_vfb 0 ao 0 na 0 vdda_dac na na (7) na 10-bit dac y23 cvideo2_vfb 0 ao 0 na 0 vdda_dac na na (7) na 10-bit dac y24 cvideo1_rset 0 aio 0 na 0 vdda_dac no na na 10-bit dac a22 cam_hs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_94 4 io hw_dbg0 5 o safe_mode 7 e18 cam_vs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_95 4 io hw_dbg1 5 o safe_mode 7 b22 cam_ xclka 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_96 4 io safe_mode 7 j19 cam_pclk 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_97 4 io hw_dbg2 5 o safe_mode 7 h24 cam_fld 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io hw_dbg3 5 o gpio_98 4 io safe_mode 7 ab18 cam_d0 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_99 4 i safe_mode 7 ac18 cam_d1 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_100 4 i safe_mode 7 g19 cam_d2 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_101 4 io hw_dbg4 5 o safe_mode 7 f19 cam_d3 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_102 4 io hw_dbg5 5 o safe_mode 7 g20 cam_d4 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_103 4 io hw_dbg6 5 o safe_mode 7 b21 cam_d5 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_104 4 io hw_dbg7 5 o safe_mode 7 l24 cam_d6 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_105 4 i safe_mode 7 k24 cam_d7 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_106 4 i safe_mode 7 j23 cam_d8 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_107 4 i safe_mode 7 70 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] k23 cam_d9 0 i l l 7 vdds yes na pu/ pd lvcmos gpio_108 4 i safe_mode 7 f21 cam_d10 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_109 4 io hw_dbg8 5 o safe_mode 7 g21 cam_d11 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_110 4 io hw_dbg9 5 o safe_mode 7 c22 cam_ xclkb 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_111 4 io safe_mode 7 f18 cam_wen 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_ shutter 2 o gpio_167 4 io hw_dbg10 5 o safe_mode 7 j20 cam_ strobe 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_126 4 io hw_dbg11 5 o safe_mode 7 v20 mcbsp2_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_116 4 io safe_mode 7 t21 mcbsp2_ clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_117 4 io safe_mode 7 v19 mcbsp2_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_118 4 io safe_mode 7 r20 mcbsp2_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_119 4 io safe_mode 7 m23 mmc1_clk 0 o l l 7 vdds_mmc1 (1 yes 1 pu/ pd (4) lvcmos 4) gpio_120 (5) 4 io safe_mode 7 l23 mmc1_cmd 0 io l l 7 vdds_mmc1 (1 yes 1 pu/ pd (4) lvcmos 4) gpio_121 (5) 4 io safe_mode 7 m22 mmc1_dat0 0 io l l 7 vdds_mmc1 (1 yes 1 pu/ pd (4) lvcmos 4) gpio_122 (5) 4 io safe_mode 7 m21 mmc1_dat1 0 io l l 7 vdds_mmc1 (1 yes 1 pu/ pd (4) lvcmos 4) gpio_123 (5) 4 io safe_mode 7 m20 mmc1_dat2 0 io l l 7 vdds_mmc1 (1 yes 1 pu/ pd (4) lvcmos 4) gpio_124 (5) 4 io safe_mode 7 n23 mmc1_dat3 0 io l l 7 vdds_mmc1 (1 yes 1 pu/ pd (4) lvcmos 4) copyright ? 2010 C 2011, texas instruments incorporated terminal description 71 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] gpio_125 (5) 4 io safe_mode 7 n22 gpio_126 (5) 4 io l l 7 vdds _x yes 1 pu/ pd (4) lvcmos safe_mode 7 p24 gpio_129 (5) 4 io l l 7 vdds _x yes 1 pu/ pd (4) lvcmos safe_mode 7 y1 mmc2_clk 0 o l l 7 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io gpio_130 4 io safe_mode 7 ab5 mmc2_cmd 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_ simo 1 io gpio_131 4 io safe_mode 7 ab3 mmc2_ dat0 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 1 io gpio_132 4 io safe_mode 7 y3 mmc2_ dat1 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_133 4 io safe_mode 7 w3 mmc2_ dat2 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o gpio_134 4 io safe_mode 7 v3 mmc2_ dat3 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io gpio_135 4 io safe_mode 7 ab2 mmc2_ dat4 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat0 1 o mmc3_dat0 3 io gpio_136 4 io safe_mode 7 aa2 mmc2_ dat5 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat1 1 o cam_global_reset 2 io mmc3_dat1 3 io gpio_137 4 io mm3_rxdp 6 io safe_mode 7 y2 mmc2_dat6 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_cmd 1 o cam_shutter 2 o mmc3_dat2 3 io gpio_138 4 io safe_mode 7 aa1 mmc2_dat7 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_clkin 1 i mmc3_dat3 3 io gpio_139 4 io mm3_rxdm 6 io safe_mode 7 v6 mcbsp3_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_cts 1 i 72 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] gpio_140 4 io safe_mode 7 v5 mcbsp3_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos uart2_rts 1 o gpio_141 4 io safe_mode 7 w4 mcbsp3_ clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_tx 1 o gpio_142 4 io safe_mode 7 v4 mcbsp3_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_rx 1 i gpio_143 4 io safe_mode 7 w7 uart1_tx 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_148 4 io safe_mode 7 w6 uart1_rts 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_149 4 io safe_mode 7 ac2 uart1_cts 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_150 4 io safe_mode 7 v7 uart1_rx 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcbsp1_ clkr 2 io mcspi4_clk 3 io gpio_151 4 io safe_mode 7 w19 mcbsp1_ clkr 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_clk 1 io gpio_156 4 io safe_mode 7 ab20 mcbsp1_fsr 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io gpio_157 4 io safe_mode 7 w18 mcbsp1_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_ simo 1 io mcbsp3_dx 2 io gpio_158 4 io safe_mode 7 y18 mcbsp1_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_ somi 1 io mcbsp3_dr 2 i gpio_159 4 io safe_mode 7 aa18 mcbsp_clks 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_ shutter 2 o gpio_160 4 io uart1_cts 5 i safe_mode 7 aa19 mcbsp1_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_cs0 1 io mcbsp3_fsx 2 io gpio_161 4 io copyright ? 2010 C 2011, texas instruments incorporated terminal description 73 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] safe_mode 7 v18 mcbsp1_ clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcbsp3_ clkx 2 io gpio_162 4 io safe_mode 7 a23 uart3_cts_ rctx 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_163 4 io safe_mode 7 b23 uart3_rts_ sd 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_164 4 io safe_mode 7 b24 uart3_rx_ irrx 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_165 4 io safe_mode 7 c23 uart3_tx_ irtx 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_166 4 io safe_mode 7 r21 hsusb0_clk 0 i l l 7 vdds yes 8 pu/ pd lvcmos gpio_120 4 io safe_mode 7 r23 hsusb0_stp 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_121 4 io safe_mode 7 p23 hsusb0_dir 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_122 4 io safe_mode 7 r22 hsusb0_nxt 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_124 4 io safe_mode 7 t24 hsusb0_ data0 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_tx_ irtx 2 o gpio_125 4 io uart2_tx 5 o safe_mode 7 t23 hsusb0_ data1 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rx_ irrx 2 i gpio_130 4 io uart2_rx 5 i safe_mode 7 u24 hsusb0_ data2 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rts_ sd 2 o gpio_131 4 io uart2_rts 5 o safe_mode 7 u23 hsusb0_ data3 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_cts_ rctx 2 io gpio_169 4 io uart2_cts 5 i safe_mode 7 w24 hsusb0_ data4 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_188 4 io safe_mode 7 v23 hsusb0_ data5 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_189 4 io safe_mode 7 74 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] w23 hsusb0_ data6 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_190 4 io safe_mode 7 t22 hsusb0_ data7 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_191 4 io safe_mode 7 k20 i2c1_scl 0 od h h 0 vdds na 3 pu/ pd (10) (11) open drain k21 i2c1_sda 0 iod h h 0 vdds yes 3 pu/ pd (10) (11) open drain ac15 i2c2_scl 0 od h h 7 vdds yes 3 pu/ pd (10) (12) open drain gpio_168 4 io 4 safe_mode 7 ac14 i2c2_sda 0 iod h h 7 vdds yes 3 pu/ pd (10) (12) open drain gpio_183 4 io 4 safe_mode 7 ac13 i2c3_scl 0 od h h 7 vdds yes 3 pu/ pd (10) (12) open drain gpio_184 4 io 4 safe_mode 7 ac12 i2c3_sda 0 iod h h 7 vdds yes 3 pu/ pd (10) (12) open drain gpio_185 4 io 4 safe_mode 7 y16 i2c4_scl 0 od h h 0 vdds yes 3 pu/ pd (10) (11) open drain sys_nvmode1 1 o 4 safe_mode 7 y15 i2c4_sda 0 iod h h 0 vdds yes 3 pu/ pd (10) (11) open drain sys_nvmode2 1 o 4 safe_mode 7 a24 hdq_sio 0 iod h h 7 vdds yes 4 pu/ pd lvcmos sys_altclk 1 i i2c2_sccbe 2 od i2c3_sccbe 3 od gpio_170 4 io safe_mode 7 t5 mcspi1_clk 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat4 1 io gpio_171 4 io safe_mode 7 r4 mcspi1_ simo 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat5 1 io gpio_172 4 io safe_mode 7 t4 mcspi1_ somi 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dat6 1 io gpio_173 4 io safe_mode 7 t6 mcspi1_cs0 0 io h h 7 vdds yes 4 pu/ pd lvcmos mmc2_dat7 1 io gpio_174 4 io safe_mode 7 r5 mcspi1_cs3 0 o h h 7 vdds yes 4 pu/ pd lvcmos hsusb2_ data2 3 io gpio_177 4 io mm2_txdat 5 io safe_mode 7 n5 mcspi2_clk 0 io l l 7 vdds yes 4 pu/ pd lvcmos hsusb2_ data7 3 io copyright ? 2010 C 2011, texas instruments incorporated terminal description 75 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] gpio_178 4 io safe_mode 7 n4 mcspi2_ simo 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt_9_pwm_evt 1 io hsusb2_ data4 3 io gpio_179 4 io safe_mode 7 n3 mcspi2_ somi 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt_10_pwm_evt 1 io hsusb2_ data5 3 io gpio_180 4 io safe_mode 7 m5 mcspi2_cs0 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpt_11_pwm_evt 1 io hsusb2_ data6 3 io gpio_181 4 io safe_mode 7 m4 mcspi2_cs1 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpt_8_pwm_evt 1 io hsusb2_ data3 3 io gpio_182 4 io mm2_txen_n 5 io safe_mode 7 aa16 sys_32k 0 i z z 0 vdds yes na pu/ pd lvcmos ad15 sys_xtalin 0 ai z z 0 vdds yes na no analog ad14 sys_xtalout 0 ao z 0 0 vdds na na na analog y13 sys_clkreq 0 io 0 see (3) 0 vdds yes 4 pu/ pd lvcmos gpio_1 4 io safe_mode 7 w16 sys_nirq 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_0 4 io safe_mode 7 aa10 sys_nrespwron 0 i z z 0 vdds yes na no lvcmos y10 sys_nreswarm 0 iod 0 h 0 vdds yes 4 pu/ pd lvcmos gpio_30 4 io safe_mode 7 ab12 sys_boot0 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data18 3 io gpio_2 4 io safe_mode 7 ac16 sys_boot1 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data19 3 io gpio_3 4 io safe_mode 7 ad17 sys_boot2 0 i z z 0 vdds yes 8 pu/ pd lvcmos gpio_4 4 io safe_mode 7 ad18 sys_boot3 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data20 3 o gpio_5 4 io safe_mode 7 ac17 sys_boot4 0 i z z 0 vdds yes 8 pu/ pd lvcmos mmc2_dir_dat2 1 o dss_data21 3 o gpio_6 4 io 76 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] safe_mode 7 ab16 sys_boot5 0 i z z 0 vdds yes 8 pu/ pd lvcmos mmc2_dir_dat3 1 o dss_data22 3 o gpio_7 4 io safe_mode 7 aa15 sys_boot6 0 i z z 0 vdds yes 8 pu/ pd lvcmos dss_data23 3 o gpio_8 4 io safe_mode 7 ad23 sys_off_ mode 0 o 0 l 7 vdds yes 4 pu/ pd lvcmos gpio_9 4 io safe_mode 7 y7 sys_clkout1 0 o l l 7 (13) vdds yes 4 pu/ pd lvcmos gpio_10 4 io safe_mode 7 aa6 sys_clkout2 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_186 4 io safe_mode 7 ab7 jtag_ntrst 0 i l l 0 vdds yes na pu/ pd lvcmos ab6 jtag_tck 0 i l l 0 vdds yes na pu/ pd lvcmos aa7 jtag_rtck 0 o l 0 0 vdds na 4 pu/ pd lvcmos aa9 jtag_tms_tmsc 0 io h h 0 vdds yes 4 pu/ pd lvcmos ab10 jtag_tdi 0 i h h 0 vdds yes na pu/ pd lvcmos ab9 jtag_tdo 0 o l z 0 vdds na 4 pu/ pd lvcmos ac24 jtag_emu0 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_11 4 io safe_mode 7 ad24 jtag_emu1 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_31 4 io safe_mode 7 ac1 etk_clk 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcbsp5_ clkx 1 io mmc3_clk 2 o hsusb1_stp 3 o gpio_12 4 io mm1_rxdp 5 io hw_dbg0 7 o ad3 etk_ctl 0 o h h 4 vdds yes 4 pu/ pd lvcmos mmc3_cmd 2 io hsusb1_clk 3 o gpio_13 4 io hw_dbg1 7 o ad6 etk_d0 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_ simo 1 io mmc3_dat4 2 io hsusb1_ data0 3 io gpio_14 4 io mm1_rxrcv 5 io hw_dbg2 7 o ac6 etk_d1 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 1 io hsusb1_ data1 3 io gpio_15 4 io mm1_txse0 5 io copyright ? 2010 C 2011, texas instruments incorporated terminal description 77 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] hw_dbg3 7 o ac7 etk_d2 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io hsusb1_ data2 3 io gpio_16 4 io mm1_txdat 5 io hw_dbg4 7 o ad8 etk_d3 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io mmc3_dat3 2 io hsusb1_ data7 3 io gpio_17 4 io hw_dbg5 7 o ac5 etk_d4 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dr 1 i mmc3_dat0 2 io hsusb1_ data4 3 io gpio_18 4 io hw_dbg6 7 o ad2 etk_d5 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_fsx 1 io mmc3_dat1 2 io hsusb1_ data5 3 io gpio_19 4 io hw_dbg7 7 o ac8 etk_d6 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dx 1 o mmc3_dat2 2 io hsusb1_ data6 3 io gpio_20 4 io hw_dbg8 7 o ad9 etk_d7 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o mmc3_dat7 2 io hsusb1_ data3 3 io gpio_21 4 io mm1_txen_n 5 io hw_dbg9 7 o ac4 etk_d8 0 o l l 4 vdds yes 4 pu/ pd lvcmos mmc3_dat6 2 io hsusb1_dir 3 i gpio_22 4 io hw_dbg10 7 o ad5 etk_d9 0 o l l 4 vdds yes 4 pu/ pd lvcmos mmc3_dat5 2 io hsusb1_nxt 3 i gpio_23 4 io mm1_rxdm 5 io hw_dbg11 7 o ac3 etk_d10 0 o l l 4 vdds yes 4 pu/ pd lvcmos uart1_rx 2 i hsusb2_clk 3 o gpio_24 4 io hw_dbg12 7 o ac9 etk_d11 0 o l l 4 vdds yes 4 pu/ pd lvcmos 78 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] hsusb2_stp 3 o gpio_25 4 io mm2_rxdp 5 io hw_dbg13 7 o ac10 etk_d12 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_dir 3 i gpio_26 4 io hw_dbg14 7 o ad11 etk_d13 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_nxt 3 i gpio_27 4 io mm2_rxdm 5 io hw_dbg15 7 o ac11 etk_d14 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_ data0 3 io gpio_28 4 io mm2_rxrcv 5 io hw_dbg16 7 o ad12 etk_d15 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_ data1 3 io gpio_29 4 io mm2_txse0 5 io hw_dbg17 7 o e16, f15, vdds_mem 0 pwr - - - - - - - - f16, g15, g16, h15, j6, j7, j8, k6, k7, k8 f12, f13, vdd_core 0 pwr - - - - - - - - g12, g13, h12, h13, j17, j18, k17, k18, k19, l14, l15, m14, m15, r17, r18, r19, t17, t18, t19, t20 f10, g9, vdd_mpu_iva 0 pwr - - - - - - - - g10, h9, h10, j9, j10, l11, l12, m6, m7, m8, m12, n6, n7, n8, r6, r7, r8, t7, t8, u12, u13, v12, v13, w12, w13 h8 vdds _x 0 pwr - - - - - - - - m17, m18, vdds 0 pwr - - - - - - - - m19, n17, n18, n19, u10, v9, v10, w9, w10, y9 n24 vdds_mmc1 0 pwr - - - - - - - - y12 cap_vddu_ 0 pwr - - - - - - - - wkup_logic u8 cap_vdd_sram_mpu_ 0 pwr - - - - - - - - iva h17 cap_vdd_sram_core 0 pwr - - - - - - - - g18 vdda_dplls_dll 0 pwr - - - - - - - - u17 vdda_dpll_per 0 pwr - - - - - - - - aa12 vdds_sram 0 pwr - - - - - - - - aa13 vdda_wkup_bg_bb 0 pwr - - - - - - - - copyright ? 2010 C 2011, texas instruments incorporated terminal description 79 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) (continued) ball pin name [2] mode [3] type [4] ball reset ball reset reset rel. power [8] hys [9] buffer pullup io cell [12] number [1] state [5] rel. state mode [7] strength /down [6] (ma) [10] type [11] n21 cap_vdd_bb_mpu_iv 0 pwr - - - - - - - - a n20 cap_vddu_array 0 pwr - - - - - - - - ab15 vssa_dac 0 gnd - - - - - - - - ab13 vdda_dac 0 pwr - - - - - - - - h11, h14, vss 0 gnd - - - - - - - - h16, j11, j12, j13, j14, j15, j16, k10, k11, k14, k15, l8, l10, l13, l17, m9, m10, m11, m13, m16, n9, n10, n11, n12, n13, n14, n15, n16, p8, p10, p11, p12, p13, p14, p15, p17, r10, r11, r14, r15, t9, t10, t11, t12, t13, t14, t15, t16, u9, u11, u14, u15, u16, v15, v16 ad1, a1, a2, no connect (2) - - - - - - - - - - b1 w15 sys_xtalgnd 0 gnd - - - - - - - - (1) na in this table stands for "not applicable". (2) pins labeled as "no connect" must be left unconnected. any connections to these pins may result in unpredictable behavior. (3) depending on the sys_clkreq direction the corresponding reset released state value can be: C z if sys_clkreq is used as input C 1 if sys_clkreq is used as output for a full description of the sys_clkreq control, see power, reset, and clock management chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (4) pu = [50 to 100 k ] per default or [10 to 50 k ] according to the selected mode. for a full description of the pull-up drive strength programming, see the prg_sdmmc_pustrength configuration register bit field in the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). pd: 30 to 150 k . (5) the usage of this gpio is strongly restricted. for more information, see the general-purpose interface chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) the drive strength is fixed regardless of the load. the driver is designed to drive 75 for video applications. (7) in buffer mode, the drive strength is fixed regardless of the load. the driver is designed to drive 75 for video applications. in bypass mode, the drive strength is 0.47 ma. (8) the drive strength of these ios is set according to the programmable load range: 2 pf to 4 pf per default or 4 pf to 12 pf. for a full description of the drive strength programming, see the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (9) in the safe_mode_out1, the buffer is configured to drive 1. (10) the pullup and pulldown can be either the standard lvcmos 100- a drive strength or the i2c pullup and pulldown described below: nominal resistance = 1.66 k in high-speed mode with a load range of 5 pf to 12 pf, 4.5 k in standard / fast mode with a load range of 5 pf to 15 pf. (11) the default buffer configuration is high-speed i2c point-to-point mode using internal pullup. for a full description of the pull drive strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the control_prog_io1, control_prog_io_wkup1 control modules in the system control module / scm programming model / feature settings section and the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) to modify the io settings if required by the targeted interface application. (12) the default buffer configuration is standard lvcmos mode (non-i2c). for a full description of the pull drive strength programming, see padconfs bits of control_padconf_x control modules (standard lvcmos mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the control_prog_io2, control_prog_io3 control modules (i2c mode) in the system control module chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) to modify the io settings if required by the targeted interface application. (13) mux0 if sys_boot6 is pulled down (clock master). 80 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (14) if mmc1 functional signals are enabled, vdds_mmc1 for mmc1 must be supplied by a dedicated power source. if mmc1 functional signals are disabled, other multiplexed cmos signals of the interface can be enabled. the interface can be supplied by the same power source as vdds. the vdds power source supplies the vdds_mmc1 ball. if neither mmc1 functional balls or cmos signals are enabled, the interface balls are left unconnected with its associated power supply (vdda/vssa) grounded. for the corresponding setting of the pbiaslitepwrdnz0 bit, see the system control module / scm programming model / extended-drain i/os and pbias cells programming guide section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). copyright ? 2010 C 2011, texas instruments incorporated terminal description 81 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 2.4 multiplexing characteristics table 2-4 provides a description of the multiplexing on the cbp, cbc, and cus packages, respectively. note : the following does not take into account subsystem pin multiplexing options. subsystem pin multiplexing options are described in section 2.5 , signal description. for more information, see the system control module / system control module functional description / pad functional multiplexing and configuration section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-4. multiplexing characteristics cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top na j2 na d1 d7 sdrc_d0 na j1 na g1 c5 sdrc_d1 na g2 na g2 c6 sdrc_d2 na g1 na e1 b5 sdrc_d3 na f2 na d2 d9 sdrc_d4 na f1 na e2 d10 sdrc_d5 na d2 na b3 c7 sdrc_d6 na d1 na b4 b7 sdrc_d7 na b13 na a10 b11 sdrc_d8 na a13 na b11 c12 sdrc_d9 na b14 na a11 b12 sdrc_d10 na a14 na b12 d13 sdrc_d11 na b16 na a16 c13 sdrc_d12 na a16 na a17 b14 sdrc_d13 na b19 na b17 a14 sdrc_d14 na a19 na b18 b15 sdrc_d15 na b3 na b7 c9 sdrc_d16 na a3 na a5 e12 sdrc_d17 na b5 na b6 b8 sdrc_d18 na a5 na a6 b9 sdrc_d19 na b8 na a8 c10 sdrc_d20 na a8 na b9 b10 sdrc_d21 na b9 na a9 d12 sdrc_d22 na a9 na b10 e13 sdrc_d23 na b21 na c21 e15 sdrc_d24 na a21 na d20 d15 sdrc_d25 na d22 na b19 c15 sdrc_d26 na d23 na c20 b16 sdrc_d27 na e22 na d21 c16 sdrc_d28 na e23 na e20 d16 sdrc_d29 na g22 na e21 b17 sdrc_d30 na g23 na g21 b18 sdrc_d31 na ab21 na aa18 c18 sdrc_ba0 na ac21 na v20 d18 sdrc_ba1 na n22 na g20 a4 sdrc_a0 na n23 na k20 b4 sdrc_a1 na p22 na j20 d6 sdrc_a2 na p23 na j21 b3 sdrc_a3 na r22 na u21 b2 sdrc_a4 na r23 na r20 c3 sdrc_a5 na t22 na m21 e3 sdrc_a6 na t23 na m20 f6 sdrc_a7 na u22 na n20 e10 sdrc_a8 na u23 na k21 e9 sdrc_a9 82 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top na v22 na y16 e7 sdrc_a10 na v23 na n21 g6 sdrc_a11 na w22 na r21 g7 sdrc_a12 na w23 na aa15 f7 sdrc_a13 na y22 na y12 f9 sdrc_a14 na m22 na t21 a19 sdrc_ncs0 na m23 na t20 b19 sdrc_ncs1 na a11 na a12 a10 sdrc_clk na b11 na b13 a11 sdrc_nclk na j22 na y15 b20 sdrc_cke0 safe_mo de_out1 na j23 na y13 c20 sdrc_cke1 safe_mo de_out1 na l23 na v21 d19 sdrc_nras na l22 na u20 c19 sdrc_ncas na k23 na y18 a20 sdrc_nwe na c1 na h1 b6 sdrc_dm0 na a17 na a14 b13 sdrc_dm1 na a6 na a4 a7 sdrc_dm2 na a20 na a18 a16 sdrc_dm3 na c2 na c2 a5 sdrc_dqs0 na b17 na b15 a13 sdrc_dqs1 na b6 na b8 a8 sdrc_dqs2 na b20 na a19 a17 sdrc_dqs3 n4 ac15 j2 na k4 gpmc_a1 gpio_34 safe_mo de m4 ab15 h1 na k3 gpmc_a2 gpio_35 safe_mo de l4 ac16 h2 na k2 gpmc_a3 gpio_36 safe_mo de k4 ab16 g2 na j4 gpmc_a4 gpio_37 safe_mo de t3 ac17 f1 na j3 gpmc_a5 gpio_38 safe_mo de r3 ab17 f2 na j2 gpmc_a6 gpio_39 safe_mo de n3 ac18 e1 na j1 gpmc_a7 gpio_40 safe_mo de m3 ab18 e2 na h1 gpmc_a8 gpio_41 safe_mo de l3 ac19 d1 na h2 gpmc_a9 sys_ndmareq gpio_42 safe_mo 2 de k3 ab19 d2 na g2 gpmc_a10 sys_ndmareq gpio_43 safe_mo 3 de na ac20 a4 na na gpmc_a11 safe_mo de k1 m2 aa2 u2 l2 gpmc_d0 l1 m1 aa1 u1 m1 gpmc_d1 l2 n2 ac2 v2 m2 gpmc_d2 p2 n1 ac1 v1 n2 gpmc_d3 t1 r2 ae5 aa3 m3 gpmc_d4 v1 r1 ad6 aa4 p1 gpmc_d5 v2 t2 ad5 y3 p2 gpmc_d6 w2 t1 ac5 y4 r1 gpmc_d7 h2 ab3 v1 r1 r2 gpmc_d8 gpio_44 safe_mo de k2 ac3 y1 t1 t2 gpmc_d9 gpio_45 safe_mo de p1 ab4 t1 n1 u1 gpmc_d10 gpio_46 safe_mo de copyright ? 2010 C 2011, texas instruments incorporated terminal description 83 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top r1 ac4 u2 p2 r3 gpmc_d11 gpio_47 safe_mo de r2 ab6 u1 p1 t3 gpmc_d12 gpio_48 safe_mo de t2 ac6 p1 m1 u2 gpmc_d13 gpio_49 safe_mo de w1 ab7 l2 j2 v1 gpmc_d14 gpio_50 safe_mo de y1 ac7 m2 k2 v2 gpmc_d15 gpio_51 safe_mo de g4 y2 ad8 aa8 e2 gpmc_ncs0 h3 y1 ad1 w1 na gpmc_ncs1 gpio_52 safe_mo de v8 na a3 na na gpmc_ncs2 gpio_53 safe_mo de u8 na b6 na d2 gpmc_ncs3 sys_ndmareq gpio_54 safe_mo 0 de t8 na b4 na f4 gpmc_ncs4 sys_ndmareq mcbsp4_clkx gpt_9_pwm gpio_55 safe_mo 1 _evt de r8 na c4 na g5 gpmc_ncs5 sys_ndmareq mcbsp4_dr gpt_10_pw gpio_56 safe_mo 2 m_evt de p8 na b5 na f3 gpmc_ncs6 sys_ndmareq mcbsp4_dx gpt_11_pw gpio_57 safe_mo 3 m_evt de n8 na c5 na g4 gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt_8_pwm gpio_58 safe_mo _evt de t4 w2 n1 l1 w2 gpmc_clk gpio_59 safe_mo de f3 w1 ad10 aa9 f1 gpmc_nadv_a le g2 v2 n2 l2 f2 gpmc_noe f4 v1 m1 k1 g3 gpmc_nwe g3 ac12 k2 na k5 gpmc_nbe0_c gpio_60 safe_mo le de u3 na j1 na l1 gpmc_nbe1 gpio_61 safe_mo de h1 ab10 ac6 y5 e1 gpmc_nwp gpio_62 safe_mo de m8 ab12 ac11 y10 c1 gpmc_wait0 l8 ac10 ac8 y8 na gpmc_wait1 gpio_63 safe_mo de k8 na b3 na na gpmc_wait2 uart4_tx gpio_64 safe_mo de j8 na c6 na c2 gpmc_wait3 sys_ndmareq uart4_rx (3) gpio_65 safe_mo 1 de d28 na g25 na g22 dss_pclk gpio_66 hw_dbg12 safe_mo de d26 na k24 na e22 dss_hsync gpio_67 hw_dbg13 safe_mo de d27 na m25 na f22 dss_vsync gpio_68 safe_mo de e27 na f26 na j21 dss_acbias gpio_69 safe_mo de ag22 na ae21 na ac19 dss_data0 uart1_cts gpio_70 safe_mo de ah22 na ae22 na ab19 dss_data1 uart1_rts gpio_71 safe_mo de ag23 na ae23 na ad20 dss_data2 gpio_72 safe_mo de ah23 na ae24 na ac20 dss_data3 gpio_73 safe_mo de ag24 na ad23 na ad21 dss_data4 uart3_rx_irrx gpio_74 safe_mo de ah24 na ad24 na ac21 dss_data5 uart3_tx_irtx gpio_75 safe_mo de e26 na g26 na d24 dss_data6 uart1_tx gpio_76 hw_dbg14 safe_mo de 84 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top f28 na h25 na e23 dss_data7 uart1_rx gpio_77 hw_dbg15 safe_mo de f27 na h26 na e24 dss_data8 uart3_rx_irrx gpio_78 hw_dbg16 safe_mo de g26 na j26 na f23 dss_data9 uart3_tx_irtx gpio_79 hw_dbg17 safe_mo de ad28 na ac26 na ac22 dss_data10 gpio_80 safe_mo de ad27 na ad26 na ac23 dss_data11 gpio_81 safe_mo de ab28 na aa25 na ab22 dss_data12 gpio_82 safe_mo de ab27 na y25 na y22 dss_data13 gpio_83 safe_mo de aa28 na aa26 na w22 dss_data14 gpio_84 safe_mo de aa27 na ab26 na v22 dss_data15 gpio_85 safe_mo de g25 na l25 na j22 dss_data16 gpio_86 safe_mo de h27 na l26 na g23 dss_data17 gpio_87 safe_mo de h26 na m24 na g24 dss_data18 mcspi3_clk dss_data0 gpio_88 safe_mo de h25 na m26 na h23 dss_data19 mcspi3_simo dss_data1 gpio_89 safe_mo de e28 na f25 na d23 dss_data20 mcspi3_somi dss_data2 gpio_90 safe_mo de j26 na n24 na k22 dss_data21 mcspi3_cs0 dss_data3 gpio_91 safe_mo de ac27 na ac25 na v21 dss_data22 mcspi3_cs1 dss_data4 gpio_92 safe_mo de ac28 na ab25 na w21 dss_data23 dss_data5 gpio_93 safe_mo de w28 na v26 na aa23 cvideo2_out y28 na w26 na ab24 cvideo1_out y27 na w25 na ab23 cvideo1_vfb w27 na u24 na y23 cvideo2_vfb w26 na v23 na y24 cvideo1_rset a24 na c23 na a22 cam_hs gpio_94 hw_dbg0 safe_mo de a23 na d23 na e18 cam_vs gpio_95 hw_dbg1 safe_mo de c25 na c25 na b22 cam_xclka gpio_96 safe_mo de c27 na c26 na j19 cam_pclk gpio_97 hw_dbg2 safe_mo de c23 na b23 na h24 cam_fld cam_global_res gpio_98 hw_dbg3 safe_mo et de ag17 na ae16 na ab18 cam_d0 gpio_99 (1) safe_mo de ah17 na ae15 na ac18 cam_d1 gpio_100 (1) safe_mo de b24 na a24 na g19 cam_d2 gpio_101 hw_dbg4 safe_mo de c24 na b24 na f19 cam_d3 gpio_102 hw_dbg5 safe_mo de d24 na d24 na g20 cam_d4 gpio_103 hw_dbg6 safe_mo de a25 na c24 na b21 cam_d5 gpio_104 hw_dbg7 safe_mo de k28 na p25 na l24 cam_d6 gpio_105 (1) safe_mo de l28 na p26 na k24 cam_d7 gpio_106 (1) safe_mo de copyright ? 2010 C 2011, texas instruments incorporated terminal description 85 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top k27 na n25 na j23 cam_d8 gpio_107 (1) safe_mo de l27 na n26 na k23 cam_d9 gpio_108 (1) safe_mo de b25 na d25 na f21 cam_d10 gpio_109 hw_dbg8 safe_mo de c26 na e26 na g21 cam_d11 gpio_110 hw_dbg9 safe_mo de b26 na e25 na c22 cam_xclkb gpio_111 safe_mo de b23 na a23 na f18 cam_wen cam_shutter gpio_167 hw_dbg10 safe_mo de d25 na d26 na j20 cam_strobe gpio_126 hw_dbg11 safe_mo de ag19 na ad17 na na gpio_112 (1) safe_mo de ah19 na ad16 na na gpio_113 (1) safe_mo de ag18 na ae18 na na gpio_114 (1) safe_mo de ah18 na ae17 na na gpio_115 (1) safe_mo de p21 na u18 na v20 mcbsp2_fsx gpio_116 safe_mo de n21 na r18 na t21 mcbsp2_clkx gpio_117 safe_mo de r21 na t18 na v19 mcbsp2_dr gpio_118 safe_mo de m21 na r19 na r20 mcbsp2_dx gpio_119 safe_mo de n28 na n19 na m23 mmc1_clk gpio_120 (2) safe_mo de m27 na l18 na l23 mmc1_cmd gpio_121 (2) safe_mo de n27 na m19 na m22 mmc1_dat0 gpio_122 (2) safe_mo de n26 na m18 na m21 mmc1_dat1 gpio_123 (2) safe_mo de n25 na k18 na m20 mmc1_dat2 gpio_124 (2) safe_mo de p28 na n20 na n23 mmc1_dat3 gpio_125 (2) safe_mo de p27 na m20 na n22 gpio_126 (2) safe_mo de p26 na p17 na na gpio_127 (2) safe_mo de r27 na p18 na na gpio_128 safe_mo de r25 na p19 na p24 gpio_129 (2) safe_mo de ae2 na w10 na y1 mmc2_clk mcspi3_clk gpio_130 safe_mo de ag5 na r10 na ab5 mmc2_cmd mcspi3_simo gpio_131 safe_mo de ah5 na t10 na ab3 mmc2_dat0 mcspi3_somi gpio_132 safe_mo de ah4 na t9 na y3 mmc2_dat1 gpio_133 safe_mo de ag4 na u10 na w3 mmc2_dat2 mcspi3_cs1 gpio_134 safe_mo de af4 na u9 na v3 mmc2_dat3 mcspi3_cs0 gpio_135 safe_mo de ae4 na v10 na ab2 mmc2_dat4 mmc2_dir_dat mmc3_dat0 gpio_136 safe_mo 0 de ah3 na m3 na aa2 mmc2_dat5 mmc2_dir_dat cam_global_res mmc3_dat1 gpio_137 mm3_rxdp safe_mo 1 et de 86 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top af3 na l3 na y2 mmc2_dat6 mmc2_dir_cm cam_shutter mmc3_dat2 gpio_138 safe_mo d de ae3 na k3 na aa1 mmc2_dat7 mmc2_clkin mmc3_dat3 gpio_139 mm3_rxdm safe_mo de af6 na p3 na v6 mcbsp3_dx uart2_cts gpio_140 safe_mo de ae6 na n3 na v5 mcbsp3_dr uart2_rts gpio_141 safe_mo de af5 na u3 na w4 mcbsp3_clkx uart2_tx gpio_142 safe_mo de ae5 na w3 na v4 mcbsp3_fsx uart2_rx gpio_143 safe_mo de ab26 na y24 na na uart2_cts mcbsp3_dx gpt_9_pwm_evt gpio_144 safe_mo de ab25 na aa24 na na uart2_rts mcbsp3_dr gpt_10_pwm_e gpio_145 safe_mo vt de aa25 na ad22 na na uart2_tx mcbsp3_clkx gpt_11_pwm_e gpio_146 safe_mo vt de ad25 na ad21 na na uart2_rx mcbsp3_fsx gpt_8_pwm_evt gpio_147 safe_mo de aa8 na l4 na w7 uart1_tx gpio_148 safe_mo de aa9 na r2 na w6 uart1_rts gpio_149 safe_mo de w8 na w2 na ac2 uart1_cts gpio_150 safe_mo de y8 na h3 na v7 uart1_rx mcbsp1_clkr mcspi4_clk gpio_151 safe_mo de ae1 na v3 na na mcbsp4_clkx gpio_152 mm3_txse0 safe_mo de ad1 na u4 na na mcbsp4_dr gpio_153 mm3_rxrcv safe_mo de ad2 na r3 na na mcbsp4_dx gpio_154 mm3_txdat safe_mo de ac1 na t3 na na mcbsp4_fsx gpio_155 mm3_txen_ safe_mo n de y21 na u19 na w19 mcbsp1_clkr mcspi4_clk gpio_156 safe_mo de aa21 na v17 na ab20 mcbsp1_fsr cam_global_res gpio_157 safe_mo et de v21 na u17 na w18 mcbsp1_dx mcspi4_simo mcbsp3_dx gpio_158 safe_mo de u21 na t20 na y18 mcbsp1_dr mcspi4_somi mcbsp3_dr gpio_159 safe_mo de t21 na t19 na aa18 mcbsp_clks cam_shutter gpio_160 uart1_cts safe_mo de k26 na p20 na aa19 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 safe_mo de w21 na t17 na v18 mcbsp1_clkx mcbsp3_clkx gpio_162 safe_mo de h18 na f23 na a23 uart3_cts_rctx gpio_163 safe_mo de h19 na f24 na b23 uart3_rts_sd gpio_164 safe_mo de h20 na h24 na b24 uart3_rx_irrx gpio_165 safe_mo de h21 na g24 na c23 uart3_tx_irtx gpio_166 safe_mo de t28 na w19 na r21 hsusb0_clk gpio_120 safe_mo de t25 na u20 na r23 hsusb0_stp gpio_121 safe_mo de r28 na v19 na p23 hsusb0_dir gpio_122 safe_mo de t26 na w18 na r22 hsusb0_nxt gpio_124 safe_mo de copyright ? 2010 C 2011, texas instruments incorporated terminal description 87 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top t27 na v20 na t24 hsusb0_data0 uart3_tx_irtx gpio_125 uart2_tx safe_mo de u28 na y20 na t23 hsusb0_data1 uart3_rx_irrx gpio_130 uart2_rx safe_mo de u27 na v18 na u24 hsusb0_data2 uart3_rts_sd gpio_131 uart2_rts safe_mo de u26 na w20 na u23 hsusb0_data3 uart3_cts_rctx gpio_169 uart2_cts safe_mo de u25 na w17 na w24 hsusb0_data4 gpio_188 safe_mo de v28 na y18 na v23 hsusb0_data5 gpio_189 safe_mo de v27 na y19 na w23 hsusb0_data6 gpio_190 safe_mo de v26 na y17 na t22 hsusb0_data7 gpio_191 safe_mo de k21 na j25 na k20 i2c1_scl j21 na j24 na k21 i2c1_sda af15 na c2 na ac15 i2c2_scl gpio_168 safe_mo de ae15 na c1 na ac14 i2c2_sda gpio_183 safe_mo de af14 na ab4 na ac13 i2c3_scl gpio_184 safe_mo de ag14 na ac4 na ac12 i2c3_sda gpio_185 safe_mo de ad26 na ad15 na y16 i2c4_scl sys_nvmode1 safe_mo de ae26 na w16 na y15 i2c4_sda sys_nvmode2 safe_mo de j25 na j23 na a24 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 safe_mo de ab3 na p9 na t5 mcspi1_clk mmc2_dat4 gpio_171 safe_mo de ab4 na p8 na r4 mcspi1_simo mmc2_dat5 gpio_172 safe_mo de aa4 na p7 na t4 mcspi1_somi mmc2_dat6 gpio_173 safe_mo de ac2 na r7 na t6 mcspi1_cs0 mmc2_dat7 gpio_174 safe_mo de ac3 na r8 na na mcspi1_cs1 mmc3_cmd gpio_175 safe_mo de ab1 na r9 na na mcspi1_cs2 mmc3_clk gpio_176 safe_mo de ab2 na t8 na r5 mcspi1_cs3 hsusb2_dat gpio_177 mm2_txdat safe_mo a2 de aa3 na w7 na n5 mcspi2_clk hsusb2_dat gpio_178 safe_mo a7 de y2 na w8 na n4 mcspi2_simo gpt_9_pwm_e hsusb2_dat gpio_179 safe_mo vt a4 de y3 na u8 na n3 mcspi2_somi gpt_10_pwm_ hsusb2_dat gpio_180 safe_mo evt a5 de y4 na v8 na m5 mcspi2_cs0 gpt_11_pwm_ hsusb2_dat gpio_181 safe_mo evt a6 de v3 na v9 na m4 mcspi2_cs1 gpt_8_pwm_e hsusb2_dat gpio_182 mm2_txen_ safe_mo vt a3 n de ae25 na ae20 na aa16 sys_32k ae17 na af19 na ad15 sys_xtalin af17 na af20 na ad14 sys_xtalout af25 na w15 na y13 sys_clkreq gpio_1 safe_mo de af26 na v16 na w16 sys_nirq gpio_0 safe_mo de ah25 na v13 na aa10 sys_nrespwro n 88 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top af24 na ad7 aa5 y10 sys_nreswar gpio_30 safe_mo m de ah26 na f3 na ab12 sys_boot0 dss_data18 gpio_2 safe_mo de ag26 na d3 na ac16 sys_boot1 dss_data19 gpio_3 safe_mo de ae14 na c3 na ad17 sys_boot2 gpio_4 safe_mo de af18 na e3 na ad18 sys_boot3 dss_data20 gpio_5 safe_mo de af19 na e4 na ac17 sys_boot4 mmc2_dir_dat dss_data21 gpio_6 safe_mo 2 de ae21 na g3 na ab16 sys_boot5 mmc2_dir_dat dss_data22 gpio_7 safe_mo 3 de af21 na d4 na aa15 sys_boot6 dss_data23 gpio_8 safe_mo de af22 na v12 na ad23 sys_off_mode gpio_9 safe_mo de ag25 na ae14 na y7 sys_clkout1 gpio_10 safe_mo de ae22 na w11 na aa6 sys_clkout2 gpio_186 safe_mo de aa17 na u15 na ab7 jtag_ntrst aa13 na v14 na ab6 jtag_tck aa12 na w13 na aa7 jtag_rtck aa18 na v15 na aa9 jtag_tms_tms c aa20 na u16 na ab10 jtag_tdi aa19 na y13 na ab9 jtag_tdo aa11 na y15 na ac24 jtag_emu0 gpio_11 safe_mo de aa10 na y14 na ad24 jtag_emu1 gpio_31 safe_mo de af10 na ab2 na ac1 etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hw_dbg 0 ae10 na ab3 na ad3 etk_ctl mmc3_cmd hsusb1_clk gpio_13 hw_dbg 1 af11 na ac3 na ad6 etk_d0 mcspi3_simo mmc3_dat4 hsusb1_dat gpio_14 mm1_rxrcv hw_dbg a0 2 ag12 na ad4 na ac6 etk_d1 mcspi3_somi hsusb1_dat gpio_15 mm1_txse0 hw_dbg a1 3 ah12 na ad3 na ac7 etk_d2 mcspi3_cs0 hsusb1_dat gpio_16 mm1_txdat hw_dbg a2 4 ae13 na aa3 na ad8 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_dat gpio_17 hw_dbg a7 5 ae11 na y3 na ac5 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_dat gpio_18 hw_dbg a4 6 ah9 na ab1 na ad2 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_dat gpio_19 hw_dbg a5 7 af13 na ae3 na ac8 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_dat gpio_20 hw_dbg a6 8 ah14 na ad2 na ad9 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_dat gpio_21 mm1_txen_ hw_dbg a3 n 9 af9 na aa4 na ac4 etk_d8 mmc3_dat6 hsusb1_dir gpio_22 hw_dbg 10 ag9 na v2 na ad5 etk_d9 mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hw_dbg 11 ae7 na ae4 na ac3 etk_d10 uart1_rx hsusb2_clk gpio_24 hw_dbg 12 af7 na af6 na ac9 etk_d11 hsusb2_stp gpio_25 mm2_rxdp hw_dbg 13 ag7 na ae6 na ac10 etk_d12 hsusb2_dir gpio_26 hw_dbg 14 ah7 na af7 na ad11 etk_d13 hsusb2_nxt gpio_27 mm2_rxdm hw_dbg 15 copyright ? 2010 C 2011, texas instruments incorporated terminal description 89 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top ag8 na af9 na ac11 etk_d14 hsusb2_dat gpio_28 mm2_rxrcv hw_dbg a0 16 ah8 na ae9 na ad12 etk_d15 hsusb2_dat gpio_29 mm2_txse0 hw_dbg a1 17 ac4, j4, h4, na ac21, d15, na f12, f13, vdd_core d8, ae9, d9, g11, g18, g12, g13, d15, y16, h20, m7, h12, h13, ae18, y18, m17, r20, t7, j17, j18, w18, k18, y8, y12 k17, k18, j18, ae19, k19, l14, y19, u19, l15, m14, t19, n19, m15, r17, m19, j19, r18, r19, y20, w20, t17, t18, v20, u20, t19, t20 p20, n20, k20, j20, d22, d23, ae24, m25, l25, e25 y9, w9, t9, na d13, g9, na f10, g9, g10, vdd_mpu_iva r9, m9, l9, g12, h7, k11, h9, h10, j9, j9, y10, u10, l9, m9, m10, j10, l11, l12, t10, r10, n7, n8, p10, m6, m7, m8, n10, m10, u7, u11, u13, m12, n6, n7, l10, j10, v7, v11, w9, n8, r6, r7, y11, w11, y9, y11 r8, t7, t8, k11, j11, u12, u13, w12, k13, v12, v13, y14, k14, w12, w13 j14, y15, w15, j15 u4 na d6 na n21 cap_vdd_bb_ mpu_iva aa15 na k14 na y12 cap_vddu_wk up_logic k15 na k13 na g18 vdda_dplls_dll w16 na u12 na aa12 vdds_sram ad3, ad4, na a18, ac7, a3,a15,b5,f2 m17, m18, vdds w4, af8, ac15, ac18, ,f21,l20,w21 m19, n17, ae8, af16, ac24, ad20, n18, n19, ae16, af23, ae10, c11, u10, v9, v10, ae23, f25, d9, e24, g4, w9, w10, y9 f26, ag27 j15, j18, l7, l24, m4, t4, t24, w24, y4, ab24 u1, j1, f1, ac5, p1, h1, na na e16, f15, vdds_mem j2, f2, r4, f23, e1, c23, f16, g15, b5, a5, ah6, a4, a7, a10, g16, h15, j6, b8, a8, b12, a15, a18 j7, j8, k6, a12, d16, k7, k8 c16, b18, a18, b22, a22, g28, c28 aa16 na u14 na u17 vdda_dpll_per aa14 na w14 na aa13 vdda_wkup_b g_bb 90 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-4. multiplexing characteristics (continued) cbp cbc cus mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top bottom top ag2, u2, b2, b4, b7, b10, a6, a8, a13, a7, a13, b14, h11, h14, vss ag3, w3, p3, b15, b18, ab5, ab22, c1, f1, f20, h16, j11, j3, e3, a3, c22, e2, f22, ac10, ad14, h2, h20, l21, j12, j13, j14, p4, e4, ag6, h2, p2, ab5, ad25, ae7, m2, p20, r2, j15, j16, d7, c7, v9, ab14, ab20 b2, b25, c12, w20 y6, y11, k10, k11, u9, p9, n9, d7, d10, d12, aa7, aa16 k14, k15, l8, k9, w10, d14, d18, l10, l13, v10, p10, d20, e22, g1, l17, m9, k10, d10, g8, g10, m10, m11, c10, af12, g20, g23, m13, m16, ae12, y12, h4, k1, k15, n9, n10, n11, k12, j12, k25, l10, n12, n13, y13, w13, l17, l23, n4, n14, n15, j13, d13, n10, n17, r1, n16, p8, p10, c13, w14, r4, r17, t23, p11, p12, k16, j16, u25, w1, w4, p13, p14, w17, k17, w23, y7, p15, p17, j17, w19, y10, y16, r10, r11, v19, r19, y26 r14, r15, t9, p19, l19, t10, t11, k19, d19, t12, t13, c19, af20, t14, t15, ae20, t20, t16, u9, u11, ag15, af2, u14, u15, af27, b15, u16, v15, j27, m2, m26, v16 n2, aa2, ag10, ac25, ac26, y25, w25, m20, l20, l26, g27, d21, c22, b27, a26, r20, r26 v25 na v25 na ab13 vdda_dac y26 na v24 na ab15 vssa_dac k25 na n23 na n24 vdds_mmc1 p25 na p23 na h8 vdds _x ag21 na ad19 na na vdd s ah20 na ae19 na n20 cap_vddu_arr ay ah21 na ac19 na na vss ag16 na ac16 na na vss ag20 na ad18 na na vdds m28 na l19 na na vss h28 na l20 na na vdd s v4 na n9 na u8 cap_vdd_sra m_mpu_iva l21 na k20 na h17 cap_vdd_sra m_core y17 na af23 na w15 sys_xtalgnd (1) this gpio is only an input (and not an output). (2) the usage of this gpio is strongly restricted. for more information, see the general-purpose interface chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (3) uart4 is only available on cbp and cbc packages. copyright ? 2010 C 2011, texas instruments incorporated terminal description 91 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 2.5 signal description many signals are available on multiple pins according to the software configuration of the pin multiplexing options. 1. signal name: the signal name 2. description: description of the signal 3. type: type = ball type for this specific function: C i = input C o = output C z = high-impedance C d = open drain C ds = differential C a = analog 4. ball bottom: associated ball(s) bottom 5. ball top: associated ball(s) top 6. subsystem pin multiplexing: contains a list of the pin multiplexing options at the module/subsystem level. the pin function is selected at the module/system level. note : the subsystem multiplexing signals are not described in the following tables. for more information, see the system control module / system control module functional description / pad functional multiplexing and configuration section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). 2.5.1 external memory interfaces note for more information, see memory subsystem / general-purpose memory controller / gpmc environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-5. external memory interfaces C gpmc signals description (1) signal name description [2] type ball ball ball bottom ball top ball subsystem [1] [3] bottom top (cbc pkg.) [4] (cbc pkg.) [5] bottom pin (cbp (cbp (cus multiplexing pkg.) [4] pkg.) [5] pkg.) [4] [6] gpmc_a1 gpmc output address bit 1 / o n4 / k1 ac15 / m2 j2 / aa2 na / u2 k4 / l2 - / gpmc_d0 extended multiplexed address gpmc_a17 gpmc_a2 gpmc output address bit 2 / o m4 / l1 ab15 / m1 h1 / aa1 na / u1 k3 / m1 - / gpmc_d1 extended multiplexed address gpmc_a18 gpmc_a3 gpmc output address bit 3 / o l4 / l2 ac16 / n2 h2 / ac2 na / v2 k2 / m2 - / gpmc_d2 extended multiplexed address gpmc_a19 gpmc_a4 gpmc output address bit 4 / o k4 / p2 ab16 / n1 g2 / ac1 na / v1 j4 / n2 - / gpmc_d3 extended multiplexed address gpmc_a20 gpmc_a5 gpmc output address bit 5 / o t3 / t1 ac17 / r2 f1 / ae5 na / aa3 j3 / m3 - / gpmc_d4 extended multiplexed address gpmc_a21 gpmc_a6 gpmc output address bit 6 / o r3 / v1 ab17 / r1 f2 / ad6 na / aa4 j2/ p1 - / gpmc_d5 extended multiplexed address gpmc_a22 gpmc_a7 gpmc output address bit 7 / o n3 / v2 ac18 / t2 e1 / ad5 na / y3 j1/ p2 - / gpmc_d6 extended multiplexed address gpmc_a23 gpmc_a8 gpmc output address bit 8 / o m3 / w2 ab18 / t1 e2 / ac5 na / y4 h1/ r1 - / gpmc_d7 extended multiplexed address gpmc_a24 92 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-5. external memory interfaces C gpmc signals description (1) (continued) signal name description [2] type ball ball ball bottom ball top ball subsystem [1] [3] bottom top (cbc pkg.) [4] (cbc pkg.) [5] bottom pin (cbp (cbp (cus multiplexing pkg.) [4] pkg.) [5] pkg.) [4] [6] gpmc_a9 gpmc output address bit 9 / o l3 / h2 ac19 / d1 / v1 na / r1 h2/ r2 - / gpmc_d8 extended multiplexed address ab3 gpmc_a25 gpmc_a10 gpmc output address bit 10 / o k3 / k2 ab19 / d2 / y1 t1 g2/ t2 - / gpmc_d9 extended multiplexed address ac3 gpmc_a26 gpmc_a11 gpmc output address bit 11 / o nc / p1 ac20 / a4 / t1 - / n1 na - / gpmc_d10 extended multiplexed address ab4 gpmc_a27 gpmc_a12 general-purpose memory address o r1 ac4 u2 p2 r3 gpmc_d11 bit 12 gpmc_a13 general-purpose memory address o r2 ab6 u1 p1 t3 gpmc_d12 bit 13 gpmc_a14 general-purpose memory address o t2 ac6 p1 m1 u2 gpmc_d13 bit 14 gpmc_a15 general-purpose memory address o w1 ab7 l2 j2 v1 gpmc_d14 bit 15 gpmc_a16 general-purpose memory address o y1 ac7 m2 k2 v2 gpmc_d15 bit 16 gpmc_a17 general-purpose memory address o n4 ac15 j2 na k4 gpmc_a1 bit 17 gpmc_a18 general-purpose memory address o m4 ab15 h1 na k3 gpmc_a2 bit 18 gpmc_a19 general-purpose memory address o l4 ac16 h2 na k2 gpmc_a3 bit 19 gpmc_a20 general-purpose memory address o k4 ab16 g2 na j4 gpmc_a4 bit 20 gpmc_a21 general-purpose memory address o t3 ac17 f1 na j3 gpmc_a5 bit 21 gpmc_a22 general-purpose memory address o r3 ab17 f2 na j2 gpmc_a6 bit 22 gpmc_a23 general-purpose memory address o n3 ac18 e1 na j1 gpmc_a7 bit 23 gpmc_a24 general-purpose memory address o m3 ab18 e2 na h1 gpmc_a8 bit 24 gpmc_a25 general-purpose memory address o l3 ac19 d1 na h2 gpmc_a9 bit 25 gpmc_a26 general-purpose memory address o k3 ab19 d2 na g2 gpmc_a10 bit 26 gpmc_d0 gpmc data bit 0 / multiplexed io k1 m2 aa2 u2 l2 gpmc_d0 address gpmc_a1 gpmc_d1 gpmc data bit 1 / multiplexed io l1 m1 aa1 u1 m1 gpmc_d1 address gpmc_a2 gpmc_d2 gpmc data bit 2 / multiplexed io l2 n2 ac2 v2 m2 gpmc_d2 address gpmc_a3 gpmc_d3 gpmc data bit 3 / multiplexed io p2 n1 ac1 v1 n2 gpmc_d3 address gpmc_a4 gpmc_d4 gpmc data bit 4 / multiplexed io t1 r2 ae5 aa3 m3 gpmc_d4 address gpmc_a5 gpmc_d5 gpmc data bit 5 / multiplexed io v1 r1 ad6 aa4 p1 gpmc_d5 address gpmc_a6 gpmc_d6 gpmc data bit 6 / multiplexed io v2 t2 ad5 y3 p2 gpmc_d6 address gpmc_a7 gpmc_d7 gpmc data bit 7 / multiplexed io w2 t1 ac5 y4 r1 gpmc_d7 address gpmc_a8 gpmc_d8 gpmc data bit 8 / multiplexed io h2 ab3 v1 r1 r2 gpmc_d8 address gpmc_a9 gpmc_d9 gpmc data bit 9 / multiplexed io k2 ac3 y1 t1 t2 gpmc_d9 address gpmc_a10 copyright ? 2010 C 2011, texas instruments incorporated terminal description 93 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-5. external memory interfaces C gpmc signals description (1) (continued) signal name description [2] type ball ball ball bottom ball top ball subsystem [1] [3] bottom top (cbc pkg.) [4] (cbc pkg.) [5] bottom pin (cbp (cbp (cus multiplexing pkg.) [4] pkg.) [5] pkg.) [4] [6] gpmc_d10 gpmc data bit 10 / multiplexed io p1 ab4 t1 n1 u1 gpmc_d10 address gpmc_a11 gpmc_d11 gpmc data bit 11 / multiplexed io r1 ac4 u2 p2 r3 gpmc_d11 address gpmc_a12 gpmc_d12 gpmc data bit 12 / multiplexed io r2 ab6 u1 p1 t3 gpmc_d12 address gpmc_a13 gpmc_d13 gpmc data bit 13 / multiplexed io t2 ac6 p1 m1 u2 gpmc_d13 address gpmc_a14 gpmc_d14 gpmc data bit 14 / multiplexed io w1 ab7 l2 j2 v1 gpmc_d14 address gpmc_a15 gpmc_d15 gpmc data bit 15 / multiplexed io y1 ac7 m2 k2 v2 gpmc_d15 address gpmc_a16 gpmc_ncs0 gpmc chip select bit 0 o g4 y2 ad8 aa8 e2 na gpmc_ncs1 gpmc chip select bit 1 o h3 y1 ad1 w1 na na gpmc_ncs2 gpmc chip select bit 2 o v8 na a3 na na na gpmc_ncs3 gpmc chip select bit 3 o u8 na b6 na d2 na gpmc_ncs4 gpmc chip select bit 4 o t8 na b4 na f4 na gpmc_ncs5 gpmc chip select bit 5 o r8 na c4 na g5 na gpmc_ncs6 gpmc chip select bit 6 o p8 na b5 na f3 na gpmc_ncs7 gpmc chip select bit 7 o n8 na c5 na g4 na gpmc_io_dir gpmc io direction control for use o n8 na c5 na g4 na with external transceivers gpmc_clk gpmc clock o t4 w2 n1 l1 w2 na gpmc_nadv_ale address valid or address latch o f3 w1 ad10 aa9 f1 na enable gpmc_noe output enable o g2 v2 n2 l2 f2 na gpmc_nwe write enable o f4 v1 m1 k1 g3 na gpmc_nbe0_cle lower byte enable. also used for o g3 ac12 k2 na k5 na command latch enable gpmc_nbe1 upper byte enable o u3 na j1 na l1 na gpmc_nwp flash write protect o h1 ab10 ac6 y5 e1 na gpmc_wait0 external indication of wait i m8 ab12 ac11 y10 c1 na gpmc_wait1 external indication of wait i l8 ac10 ac8 y8 na na gpmc_wait2 external indication of wait i k8 na b3 na na na gpmc_wait3 external indication of wait i j8 na c6 na c2 na (1) na in table stands for "not applicable". note for more information, see memory subsystem / sdram controller (sdrc) subsystem / sdrc subsystem environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). 94 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-6. external memory interfaces C sdrc signals description (1) signal description [2] type [3] ball ball top ball bottom ball top ball bottom name [1] bottom (cbp pkg.) (cbc pkg.) [4] (2) (cbc pkg.) [5] (cus pkg.) [4] (cbp pkg.) [5] [4] (2) sdrc_d0 sdram data bit 0 io na j2 na d1 d7 sdrc_d1 sdram data bit 1 io na j1 na g1 c5 sdrc_d2 sdram data bit 2 io na g2 na g2 c6 sdrc_d3 sdram data bit 3 io na g1 na e1 b5 sdrc_d4 sdram data bit 4 io na f2 na d2 d9 sdrc_d5 sdram data bit 5 io na f1 na e2 d10 sdrc_d6 sdram data bit 6 io na d2 na b3 c7 sdrc_d7 sdram data bit 7 io na d1 na b4 b7 sdrc_d8 sdram data bit 8 io na b13 na a10 b11 sdrc_d9 sdram data bit 9 io na a13 na b11 c12 sdrc_d10 sdram data bit 10 io na b14 na a11 b12 sdrc_d11 sdram data bit 11 io na a14 na b12 d13 sdrc_d12 sdram data bit 12 io na b16 na a16 c13 sdrc_d13 sdram data bit 13 io na a16 na a17 b14 sdrc_d14 sdram data bit 14 io na b19 na b17 a14 sdrc_d15 sdram data bit 15 io na a19 na b18 b15 sdrc_d16 sdram data bit 16 io na b3 na b7 c9 sdrc_d17 sdram data bit 17 io na a3 na a5 e12 sdrc_d18 sdram data bit 18 io na b5 na b6 b8 sdrc_d19 sdram data bit 19 io na a5 na a6 b9 sdrc_d20 sdram data bit 20 io na b8 na a8 c10 sdrc_d21 sdram data bit 21 io na a8 na b9 b10 sdrc_d22 sdram data bit 22 io na b9 na a9 d12 sdrc_d23 sdram data bit 23 io na a9 na b10 e13 sdrc_d24 sdram data bit 24 io na b21 na c21 e15 sdrc_d25 sdram data bit 25 io na a21 na d20 d15 sdrc_d26 sdram data bit 26 io na d22 na b19 c15 sdrc_d27 sdram data bit 27 io na d23 na c20 b16 sdrc_d28 sdram data bit 28 io na e22 na d21 c16 sdrc_d29 sdram data bit 29 io na e23 na e20 d16 sdrc_d30 sdram data bit 30 io na g22 na e21 b17 sdrc_d31 sdram data bit 31 io na g23 na g21 b18 sdrc_ba0 sdram bank select 0 o na ab21 na aa18 c18 sdrc_ba1 sdram bank select 1 o na ac21 na v20 d18 sdrc_a0 sdram address bit 0 o na n22 na g20 a4 sdrc_a1 sdram address bit 1 o na n23 na k20 b4 sdrc_a2 sdram address bit 2 o na p22 na j20 d6 sdrc_a3 sdram address bit 3 o na p23 na j21 b3 sdrc_a4 sdram address bit 4 o na r22 na u21 b2 sdrc_a5 sdram address bit 5 o na r23 na r20 c3 sdrc_a6 sdram address bit 6 o na t22 na m21 e3 sdrc_a7 sdram address bit 7 o na t23 na m20 f6 sdrc_a8 sdram address bit 8 o na u22 na n20 e10 sdrc_a9 sdram address bit 9 o na u23 na k21 e9 sdrc_a10 sdram address bit 10 o na v22 na y16 e7 sdrc_a11 sdram address bit 11 o na v23 na n21 g6 sdrc_a12 sdram address bit 12 o na w22 na r21 g7 sdrc_a13 sdram address bit 13 o na w23 na aa15 f7 sdrc_a14 sdram address bit 14 o na y22 na y12 f9 copyright ? 2010 C 2011, texas instruments incorporated terminal description 95 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-6. external memory interfaces C sdrc signals description (1) (continued) signal description [2] type [3] ball ball top ball bottom ball top ball bottom name [1] bottom (cbp pkg.) (cbc pkg.) [4] (2) (cbc pkg.) [5] (cus pkg.) [4] (cbp pkg.) [5] [4] (2) sdrc_ncs0 chip select 0 o na m22 na t21 a19 sdrc_ncs1 chip select 1 o na m23 na t20 b19 sdrc_clk clock io na a11 na a12 a10 sdrc_nclk clock invert o na b11 na b13 a11 sdrc_cke0 clock enable 0 o na j22 na y15 b20 sdrc_cke1 clock enable 1 o na j23 na y13 c20 sdrc_nras sdram row access o na l23 na v21 d19 sdrc_ncas sdram column o na l22 na u20 c19 address strobe sdrc_nwe sdram write enable o na k23 na y18 a20 sdrc_dm 0 data mask 0 o na c1 na h1 b6 sdrc_ dm1 data mask 1 o na a17 na a14 b13 sdrc_ dm2 data mask 2 o na a6 na a4 a7 sdrc_dm 3 data mask 3 o na a20 na a18 a16 sdrc_dqs0 data strobe 0 io na b17 na c2 a5 sdrc_dqs1 data strobe 1 io na na na b15 a13 sdrc_dqs2 data strobe 2 io na na na b8 a8 sdrc_dqs3 data strobe 3 io na b20 na a19 a17 (1) na in this table stands for "not applicable". (2) for a list of pins not supported on a particular package, see table 2-4 . 96 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 2.5.2 video interfaces table 2-7. video interfaces C cam signals description signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] cam_hs camera horizontal synchronization io a24 c23 a22 cam_vs camera vertical synchronization io a23 d23 e18 cam_xclka camera clock output a o c25 c25 b22 cam_xclkb camera clock output b o b26 e25 c22 cam_d0 camera digital image data bit 0 i ag17 ae16 ab18 cam_d1 camera digital image data bit 1 i ah17 ae15 ac18 cam_d2 camera digital image data bit 2 i b24 a24 g19 cam_d3 camera digital image data bit 3 i c24 b24 f19 cam_d4 camera digital image data bit 4 i d24 d24 g20 cam_d5 camera digital image data bit 5 i a25 c24 b21 cam_d6 camera digital image data bit 6 i k28 p25 l24 cam_d7 camera digital image data bit 7 i l28 p26 k24 cam_d8 camera digital image data bit 8 i k27 n25 j23 cam_d9 camera digital image data bit 9 i l27 n26 k23 cam_d10 camera digital image data bit 10 i b25 d25 f21 cam_d11 camera digital image data bit 11 i c26 e26 g21 cam_fld camera field identification io c23 b23 h24 cam_pclk camera pixel clock i c27 c26 j19 cam_wen camera write enable i b23 a23 f18 cam_strobe flash strobe control signal o d25 d26 j20 cam_global_reset global reset is used strobe io c23 / ah3 / aa21 b23/m3/v17 h24/ aa2/ ab20 synchronization cam_shutter mechanical shutter control signal o b23 / af3 / t21 a23 / t19/ l3 f18/ y2/ aa18 note for more information, see display subsystem / display subsystem environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-8. video interfaces C dss signals description signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] dss_pclk lcd pixel clock o d28 g25 g22 dss_hsync lcd horizontal synchronization o d26 k24 e22 dss_vsync lcd vertical synchronization o d27 m25 f22 dss_acbias ac bias control (stn) or pixel data enable (tft) output o e27 f26 j21 dss_data0 lcd pixel data bit 0 o ag22 / h26 ae21 / m24 ac19 / g24 dss_data1 lcd pixel data bit 1 o ah22 / h25 ae22 / m26 ab19 / h23 dss_data2 lcd pixel data bit 2 o ag23 / e28 ae23 / f25 ad20 / d23 dss_data3 lcd pixel data bit 3 o ah23 / j26 ae24 / n24 ac20 / k22 dss_data4 lcd pixel data bit 4 o ag24 / ac27 ad23 / ac25 ad21 / v21 dss_data5 lcd pixel data bit 5 o ah24 / ac28 ad24 / ab25 ac21 / w21 dss_data6 lcd pixel data bit 6 o e26 g26 d24 dss_data7 lcd pixel data bit 7 o f28 h25 e23 dss_data8 lcd pixel data bit 8 o f27 h26 e24 dss_data9 lcd pixel data bit 9 o g26 j26 f23 dss_data10 lcd pixel data bit 10 o ad28 ac26 ac22 copyright ? 2010 C 2011, texas instruments incorporated terminal description 97 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-8. video interfaces C dss signals description (continued) signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] dss_data11 lcd pixel data bit 11 o ad27 ad26 ac23 dss_data12 lcd pixel data bit 12 o ab28 aa25 ab22 dss_data13 lcd pixel data bit 13 o ab27 y25 y22 dss_data14 lcd pixel data bit 14 o aa28 aa26 w22 dss_data15 lcd pixel data bit 15 o aa27 ab26 v22 dss_data16 lcd pixel data bit 16 o g25 l25 j22 dss_data17 lcd pixel data bit 17 o h27 l26 g23 dss_data18 lcd pixel data bit 18 o h26 / ah26 m24 / f3 g24 / ab12 dss_data19 lcd pixel data bit 19 o h25 / ag26 m26 / d3 h23 / ac16 dss_data20 lcd pixel data bit 20 o e28 / af18 f25 / e3 d23 / ad18 dss_data21 lcd pixel data bit 21 o j26 / af19 n24 / e4 k22 / ac17 dss_data22 lcd pixel data bit 22 o ac27 / ae21 ac25 / g23 v21 / ab16 dss_data23 lcd pixel data bit 23 o ac28 / af21 ab25 / d4 w21 / aa15 table 2-9. video interfaces C rfbi signals description signal description [2] type [3] ball bottom ball bottom ball bottom subsystem pin name [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] multiplexing [6] rfbi_a0 rfbi command/data control o e27 f26 j21 dss_acbias rfbi_cs0 1st lcd chip select o d26 k24 e22 dss_hsync rfbi_da0 rfbi data bus 0 io ag22 / h26 ae21 / m24 ac19 / g24 dss_data0 rfbi_da1 rfbi data bus 1 io ah22 / h25 ae22 / m26 ab19 / h23 dss_data1 rfbi_da2 rfbi data bus 2 io ag23 / e28 ae23 / f25 ad20 / d23 dss_data2 rfbi_da3 rfbi data bus 3 io ah23 / j26 ae24 / n24 ac20 / k22 dss_data3 rfbi_da4 rfbi data bus 4 io ag24 / ac27 ad23 / ac25 ad21 / v21 dss_data4 rfbi_da5 rfbi data bus 5 io ah24 / ac28 ad24 / ab25 ac21 / w21 dss_data5 rfbi_da6 rfbi data bus 6 io e26 g26 d24 dss_data6 rfbi_da7 rfbi data bus 7 io f28 h25 e23 dss_data7 rfbi_da8 rfbi data bus 8 io f27 h26 e24 dss_data8 rfbi_da9 rfbi data bus 9 io g26 j26 f23 dss_data9 rfbi_da10 rfbi data bus 10 io ad28 ac26 ac22 dss_data10 rfbi_da11 rfbi data bus 11 io ad27 ad26 ac23 dss_data11 rfbi_da12 rfbi data bus 12 io ab28 aa25 ab22 dss_data12 rfbi_da13 rfbi data bus 13 io ab27 y25 y22 dss_data13 rfbi_da14 rfbi data bus 14 io aa28 aa26 w22 dss_data14 rfbi_da15 rfbi data bus 15 io aa27 ab26 v22 dss_data15 rfbi_rd read enable for rfbi o d28 g25 g22 dss_pclk rfbi_wr write enable for rfbi o d27 m25 f22 dss_vsync rfbi_te_vsync tearing effect removal and vsync input i g25 l25 j22 dss_data16 0 from 1st lcd rfbi_hsync0 hsync for 1st lcd i h27 l26 g23 dss_data17 rfbi_te_vsync tearing effect removal and vsync input i h26 / ah26 m24 / f3 g24 / ab12 dss_data18 1 from 2nd lcd rfbi_hsync1 hsync for 2nd lcd i h25 / ag26 m26 / d3 h23 / ac16 dss_data19 rfbi_cs1 2nd lcd chip select o e28 / af18 f25 / e3 d23 / ad18 dss_data20 98 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-10. video interfaces C tv signals description signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] cvideo1_out tv analog output composite: ao y28 w26 ab24 cvideo1_out cvideo2_out tv analog output s-video: cvideo2_out ao w28 v26 aa23 cvideo1_vfb cvideo1_vfb: feedback through external ao y27 w25 ab23 resistor to composite cvideo2_vfb cvideo2_vfb: feedback through external ao w27 u24 y23 resistor to s-video cvideo1_rset cvideo1 input reference current resistor aio w26 v23 y24 setting copyright ? 2010 C 2011, texas instruments incorporated terminal description 99 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 2.5.3 serial communication interfaces for more information, see hdq/1-wire / hdq/1-wire environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-11. serial communication interfaces C hdq/1-wire signals description signal description [2] type [3] ball bottom ball bottom ball bottom name [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] hdq_sio bidirectional hdq 1-wire control and data iod j25 j23 a24 interface. output is open drain. for more information, see multimaster high-speed i2c controller / hs i2c environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-12. serial communication interfaces C i 2 c signals description signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] inter-integrated circuit interface (i2c1) i2c1_scl od k21 j25 k20 i 2 c master serial clock. output is open drain. i2c1_sda iod j21 j24 k21 i 2 c serial bidirectional data. output is open drain. inter-integrated circuit interface (i2c3) i2c3_scl od af14 ab4 ac13 i 2 c master serial clock. output is open drain. i2c3_sda iod ag14 ac4 ac12 i 2 c serial bidirectional data. output is open drain. i2c3_sccbe serial camera control bus enable od j25 j23 a24 inter-integrated circuit interface (i2c2) i2c2_scl od af15 c2 ac15 i 2 c master serial clock. output is open drain. i2c2_sda iod ae15 c1 ac14 i 2 c serial bidirectional data. output is open drain. i2c2_sccbe serial camera control bus enable od j25 j23 a24 for more information, see power reset and clock management / prcm introduction to power management / smartreflex voltage-control overview section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-13. serial communication interfaces C smartreflex signals description (1) signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] inter-integrated circuit interface (i2c4) i2c4_scl od ad26 ad15 y16 i 2 c master serial clock. output is open drain. i2c4_sda iod ae26 w16 y15 i 2 c serial bidirectional data. output is open drain. (1) for more information on smartreflex voltage control, see the prcm chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). for more information, see multi-channel buffered serial port / mcbsp environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-14. serial communication interfaces C mcbsp lp signals description signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] multichannel serial (mcbsp lp 1) 100 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-14. serial communication interfaces C mcbsp lp signals description (continued) signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] mcbsp1_dr received serial data i u21 t20 y18 mcbsp1_clkr receive clock io y8 / y21 u19 / h3 v7 / w19 mcbsp1_fsr receive frame synchronization io aa21 v17 ab20 mcbsp1_dx transmitted serial data o v21 u17 w18 mcbsp1_clkx transmit clock io w21 t17 v18 mcbsp1_fsx transmit frame synchronization io k26 p20 aa19 mcbsp_clks external clock input (shared by mcbsp1, 2, i t21 t19 aa18 3, 4, and 5) multichannel serial (mcbsp lp 2) mcbsp2_dr received serial data i r21 t18 v19 mcbsp2_dx transmitted serial data o m21 r19 r20 mcbsp2_clkx combined serial clock io n21 r18 t21 mcbsp2_fsx combined frame synchronization io p21 u18 v20 multichannel serial (mcbsp lp 3) mcbsp3_dr received serial data i ae6 / ab25 / u21 t20 / aa24 / n3 v5 / y18 mcbsp3_dx transmitted serial data o af6 / ab26 / v21 u17 / y24 / p3 v6 / w18 mcbsp3_clkx combined serial clock io af5 / aa25 / w21 t17 / ad22 / u3 w4 / v18 mcbsp3_fsx combined frame synchronization io ae5 / ad25 / k26 p20 / ad21 / w3 v4 / aa19 multichannel serial (mcbsp lp 4) mcbsp4_dr received serial data i r8 / ad1 c4 / u4 g5 mcbsp4_dx transmitted serial data o p8 / ad2 b5 / r3 f3 mcbsp4_clkx combined serial clock io t8 / ae1 b4 / v3 f4 mcbsp4_fsx combined frame synchronization io n8 / ac1 c5 / t3 g4 multichannel serial (mcbsp lp 5) mcbsp5_dr received serial data i ae11 y3 ac5 mcbsp5_dx transmitted serial data o af13 ae3 ac8 mcbsp5_clkx combined serial clock io af10 ab2 ac1 mcbsp5_fsx combined frame synchronization io ah9 ab1 ad2 for more information, see multichannel spi / mcspi environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-15. serial communication interfaces C mcspi signals description (1) signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] multichannel serial port interface (mcspi1) mcspi1_clk spi clock io ab3 p9 t5 mcspi1_simo slave data in, master data out io ab4 p8 r4 mcspi1_somi slave data out, master data in io aa4 p7 t4 mcspi1_cs0 spi enable 0, polarity configured by io ac2 r7 t6 software mcspi1_cs1 spi enable 1, polarity configured by o ac3 r8 na software mcspi1_cs2 spi enable 2, polarity configured by o ab1 r9 na software mcspi1_cs3 spi enable 3, polarity configured by o ab2 t8 r5 software multichannel serial port interface (mcspi2) mcspi2_clk spi clock io aa3 w7 n5 mcspi2_simo slave data in, master data out io y2 w8 n4 mcspi2_somi slave data out, master data in io y3 u8 n3 mcspi2_cs0 spi enable 0, polarity configured by io y4 v8 m5 software copyright ? 2010 C 2011, texas instruments incorporated terminal description 101 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-15. serial communication interfaces C mcspi signals description (1) (continued) signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] mcspi2_cs1 spi enable 1, polarity configured by o v3 v9 m4 software multichannel serial port interface (mcspi3) mcspi3_clk spi clock io h26 / ae2 / ae13 w10 / m24 / aa3 g24 / y1 / ad8 mcspi3_simo slave data in, master data out io h25 / ag5 / af11 r10 / m26 / ac3 h23 / ab5 / ad6 mcspi3_somi slave data out, master data in io e28 / ah5 / ag12 f25 / t10 / ad4 d23 / ab3 / ac6 mcspi3_cs0 spi enable 0, polarity configured by io j26 / af4 / ah12 u9 / n24 / ad3 k22 / v3 / ac7 software mcspi3_cs1 spi enable 1, polarity configured by o ac27 / ag4 / ah14 ac25 / u10 / ad2 v21 / w3 / ad9 software multichannel serial port interface (mcspi4) mcspi4_clk spi clock io y8 / y21 u19 / h3 v7 / w19 mcspi4_simo slave data in, master data out io v21 u17 w18 mcspi4_somi slave data out, master data in io u21 t20 y18 mcspi4_cs0 spi enable 0, polarity configured by io k26 p20 aa19 software (1) na in this table stands for "not applicable". for more information, see uart/irda/cir / uart/irda/cir environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-16. serial communication interfaces C uarts signals description signal name description [2] type [3] ball bottom ball bottom ball bottom [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] universal asynchronous receiver/transmitter (uart1) uart1_cts uart1 clear to send i ag22 / w8 / t21 ae21 / t19 / w2 ac19 / ac2 / aa18 uart1_rts uart1 request to send o ah22 / aa9 ae22 / r2 w6 / ab19 uart1_rx uart1 receive data i f28 / y8 / ae7 h3 / h25 / ae4 e23 / v7 / ac3 uart1_tx uart1 transmit data o e26 / aa8 l4 / g26 d24 / w7 universal asynchronous receiver/transmitter (uart2) uart2_cts uart2 clear to send i af6 / ab26 / u26 y24/ p3/ w20 v6/ u23 uart2_rts uart2 request to send o ae6 / ab25 / u27 aa24/ n3/ v18 v5/ u24 uart2_rx uart2 receive data i ae5 / ad25/ u28 w3/ ad21/ y20 t23/ v4 uart2_tx uart2 transmit data o af5 / aa25/ t27 u3/ad22/v20 t24/ w4 universal asynchronous receiver/transmitter (uart3) / irda uart3_cts_rctx uart3 clear to send (input), io h18 / u26 w20 / f23 a23 / u23 remote tx (output) uart3_rts_sd uart3 request to send, ir enable o h19 / u27 v18 / f24 b23 / u24 uart3_rx_irrx uart3 receive data, ir and i ag24 / h20 / u28 / f27 ad23 / y20 / h24/ h26 ad21 / b24 / t23 / e24 remote rx uart3_tx_irtx uart3 transmit data, ir tx o ah24 / h21 / t27/ g26 ad24 / v20 / j29 / g24 ac21 / c23 / t24/ f23 universal asynchronous receiver/transmitter (uart4) / irda uart4_rx uart4 receive data i j8 c6 na uart4_tx uart4 transmit data o k8 b3 na for more information, see high-speed usb host subsystem and high-speed usb otg controller / high-speed usb host subsystem / high-speed usb host subsystem environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-17. serial communication interfaces C usb signals description section 4.3.6 signal name description [2] type ball bottom ball bottom ball bottom [1] [3] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] high-speed universal serial bus interface (hsusb0) 102 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-17. serial communication interfaces C usb signals description section 4.3.6 (continued) signal name description [2] type ball bottom ball bottom ball bottom [1] [3] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] hsusb0_clk dedicated for external transceiver 60-mhz clock input to phy i t28 w19 r21 hsusb0_stp dedicated for external transceiver stop signal o t25 u20 r23 hsusb0_dir dedicated for external transceiver data direction control from i r28 v19 p23 phy hsusb0_nxt dedicated for external transceiver next signal from phy i t26 w18 r22 hsusb0_data0 dedicated for external transceiver bidirectional data bus io t27 v20 t24 hsusb0_data1 dedicated for external transceiver bidirectional data bus io u28 y20 t23 hsusb0_data2 dedicated for external transceiver bidirectional data bus io u27 v18 u24 hsusb0_data3 dedicated for external transceiver bidirectional data bus io u26 w20 u23 hsusb0_data4 dedicated for external transceiver bidirectional data bus io u25 w17 w24 additional signals for 12-pin ulpi operation hsusb0_data5 dedicated for external transceiver bidirectional data bus io v28 y18 v23 additional signals for 12-pin ulpi operation hsusb0_data6 dedicated for external transceiver bidirectional data bus io v27 y19 w23 additional signals for 12-pin ulpi operation hsusb0_data7 dedicated for external transceiver bidirectional data bus io v26 y17 t22 additional signals for 12-pin ulpi operation mm_fsusb3 mm3_rxdm vminus receive data (not used in 3- or 4-pin configurations) io ae3 k3 na mm3_rxdp vplus receive data (not used in 3- or 4-pin configurations) io ah3 m3 na mm3_rxrcv differential receiver signal input (not used in 3-pin mode) io ad1 u4 na mm3_txse0 single-ended zero. used as vm in 4-pin vp_vm mode. io ae1 v3 na mm3_txdat usb data. used as vp in 4-pin vp_vm mode. io ad2 r3 na mm3_txen_n transmit enable io ac1 t3 na mm_fsusb2 mm2_rxdm vminus receive data (not used in 3- or 4-pin configurations) io ah7 af7 ad11 mm2_rxdp vplus receive data (not used in 3- or 4-pin configurations) io af7 af6 ac9 mm2_rxrcv differential receiver signal input (not used in 3-pin mode) io ag8 af9 ac11 mm2_txse0 single-ended zero. used as vm in 4-pin vp_vm mode. io ah8 ae9 ad12 mm2_txdat usb data. used as vp in 4-pin vp_vm mode. io ab2 t8 r5 mm2_txen_n transmit enable io v3 v9 m4 mm_fsusb1 mm1_rxdm vminus receive data (not used in 3- or 4-pin configurations) io ag9 v2 ad5 mm1_rxdp vplus receive data (not used in 3- or 4-pin configurations) io af10 ab2 ac1 mm1_rxrcv differential receiver signal input (not used in 3-pin mode) io af11 ac3 ad6 mm1_txse0 single-ended zero. used as vm in 4-pin vp_vm mode. io ag12 ad4 ac6 mm1_txdat usb data. used as vp in 4-pin vp_vm mode. io ah12 ad3 ac7 mm1_txen_n transmit enable io ah14 ad2 ad9 hsusb2 hsusb2_clk dedicated for external transceiver 60-mhz clock input to phy o ae7 ae4 ac3 hsusb2_stp dedicated for external transceiver stop signal o af7 af6 ac9 hsusb2_dir dedicated for external transceiver data direction control from i ag7 ae6 ac10 phy hsusb2_nxt dedicated for external transceiver next signal from phy i ah7 af7 ad11 hsusb2_data0 dedicated for external transceiver bidirectional data bus io ag8 af9 ac11 hsusb2_data1 dedicated for external transceiver bidirectional data bus io ah8 ae9 ad12 hsusb2_data2 dedicated for external transceiver bidirectional data bus io ab2 t8 r5 hsusb2_data3 dedicated for external transceiver bidirectional data bus io v3 v9 m4 hsusb2_data4 dedicated for external transceiver bidirectional data bus io y2 w8 n4 additional signals for 12-pin ulpi operation hsusb2_data5 dedicated for external transceiver bidirectional data bus io y3 u8 n3 additional signals for 12-pin ulpi operation hsusb2_data6 dedicated for external transceiver bidirectional data bus io y4 v8 m5 additional signals for 12-pin ulpi operation copyright ? 2010 C 2011, texas instruments incorporated terminal description 103 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-17. serial communication interfaces C usb signals description section 4.3.6 (continued) signal name description [2] type ball bottom ball bottom ball bottom [1] [3] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] hsusb2_data7 dedicated for external transceiver bidirectional data bus io aa3 w7 n5 additional signals for 12-pin ulpi operation hsusb1 hsusb1_clk dedicated for external transceiver 60-mhz clock input to phy o ae10 ab3 ad3 hsusb1_stp dedicated for external transceiver stop signal o af10 ab2 ac1 hsusb1_dir dedicated for external transceiver data direction control from i af9 aa4 ac4 phy hsusb1_nxt dedicated for external transceiver next signal from phy i ag9 v2 ad5 hsusb1_data0 dedicated for external transceiver bidirectional data bus io af11 ac3 ad6 hsusb1_data1 dedicated for external transceiver bidirectional data bus io ag12 ad4 ac6 hsusb1_data2 dedicated for external transceiver bidirectional data bus io ah12 ad3 ac7 hsusb1_data3 dedicated for external transceiver bidirectional data bus io ah14 ad2 ad9 hsusb1_data4 dedicated for external transceiver bidirectional data bus io ae11 y3 ac5 additional signals for 12-pin ulpi operation hsusb1_data5 dedicated for external transceiver bidirectional data bus io ah9 ab1 ad2 additional signals for 12-pin ulpi operation hsusb1_data6 dedicated for external transceiver bidirectional data bus io af13 ae3 ac8 additional signals for 12-pin ulpi operation hsusb1_data7 dedicated for external transceiver bidirectional data bus io ae13 aa3 ad8 additional signals for 12-pin ulpi operation ? na in this table stands for "not applicable". ? this pin is not supported on the cus package. 104 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 2.5.4 removable media interfaces for more information, see mmc/sdio card interface / mmc/sdio environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-18. removable media interfaces C mmc/sdio signals description signal name description [2] type ball bottom ball bottom ball bottom [1] [3] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] multimedia memory card (mmc1) / secure digital io (sdio1) mmc1_clk mmc/sd output clock o n28 n19 m23 mmc1_cmd mmc/sd command signal io m27 l18 l23 mmc1_dat0 mmc/sd card data bit 0 / spi serial input io n27 m19 m22 mmc1_dat1 mmc/sd card data bit 1 io n26 m18 m21 mmc1_dat2 mmc/sd card data bit 2 io n25 k18 m20 mmc1_dat3 mmc/sd card data bit 3 io p28 n20 n23 multimedia memory card (mmc2) / secure digital io (sdio2) mmc2_clk mmc/sd output clock o ae2 w10 y1 mmc2_dir_dat0 direction control for dat0 signal case an external o ae4 v10 ab2 transceiver used mmc2_dir_dat1 direction control for dat1 and dat3 signals case an o ah3 m3 aa2 external transceiver used mmc2_dir_dat2 direction control for dat2 signal case an external o af19 e4 ac17 transceiver used mmc2_dir_dat3 direction control for dat4, dat5, dat6, and dat7 o ae21 g3 ab16 signals case an external transceiver used mmc2_clkin mmc/sd input clock i ae3 k3 aa1 mmc2_dat0 mmc/sd card data bit 0 io ah5 t10 ab3 mmc2_dat1 mmc/sd card data bit 1 io ah4 t9 y3 mmc2_dat2 mmc/sd card data bit 2 io ag4 u10 w3 mmc2_dat3 mmc/sd card data bit 3 io af4 u9 v3 mmc2_dat4 mmc/sd card data bit 4 io ae4 / ab3 p9 / v10 ab2 / t5 mmc2_dat5 mmc/sd card data bit 5 io ah3 / ab4 m3/p8 aa2 / r4 mmc2_dat6 mmc/sd card data bit 6 io af3 / aa4 l3/p7 y2 / t4 mmc2_dat7 mmc/sd card data bit 7 io ae3 / ac2 k3/r7 aa1 / t6 mmc2_dir_cmd direction control for cmd signal case an external o af3 l3 y2 transceiver is used mmc2_cmd mmc/sd command signal io ag5 r10 ab5 multimedia memory card (mmc3) / secure digital io (sdio3) mmc3_clk mmc/sd output clock o ab1 / af10 r9 / ab2 ac1 mmc3_cmd mmc/sd command signal io ac3 / ae10 r8 / ab3 ad3 mmc3_dat0 mmc/sd card data bit 0 / spi serial input io ae4 / ae11 v10 / y3 ab2 / ac5 mmc3_dat1 mmc/sd card data bit 1 io ah3 / ah9 m3/ab1 aa2 / ad2 mmc3_dat2 mmc/sd card data bit 2 io af3 / af13 l3/ae3 y2 / ac8 mmc3_dat3 mmc/sd card data bit 3 io ae3 / ae13 k3/aa3 aa1 / ad8 mmc3_dat4 mmc/sd card data bit 4 io af11 ac3 ad6 mmc3_dat5 mmc/sd card data bit 5 io ag9 v2 ad5 mmc3_dat6 mmc/sd card data bit 6 io af9 aa4 ac4 mmc3_dat7 mmc/sd card data bit 7 io ah14 ad2 ad9 copyright ? 2010 C 2011, texas instruments incorporated terminal description 105 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 2.5.5 test interfaces table 2-19. test interfaces C etk signals description signal name [1] description [2] type [3] ball bottom ball bottom ball bottom (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] etk_ctl etk trace ctl o ae10 ab3 ad3 etk_clk etk trace clock o af10 ab2 ac1 etk_d0 etk data 0 o af11 ac3 ad6 etk_d1 etk data 1 o ag12 ad4 ac6 etk_d2 etk data 2 o ah12 ad3 ac7 etk_d3 etk data 3 o ae13 aa3 ad8 etk_d4 etk data 4 o ae11 y3 ac5 etk_d5 etk data 5 o ah9 ab1 ad2 etk_d6 etk data 6 o af13 ae3 ac8 etk_d7 etk data 7 o ah14 ad2 ad9 etk_d8 etk data 8 o af9 aa4 ac4 etk_d9 etk data 9 o ag9 v2 ad5 etk_d10 etk data 10 o ae7 ae4 ac3 etk_d11 etk data 11 o af7 af6 ac9 etk_d12 etk data 12 o ag7 ae6 ac10 etk_d13 etk data 13 o ah7 af7 ad11 etk_d14 etk data 14 o ag8 af9 ac11 etk_d15 etk data 15 o ah8 ae9 ad12 table 2-20. test interfaces C jtag signals description signal name [1] description [2] type [3] ball bottom ball bottom ball bottom (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] jtag_ntrst test reset i aa17 u15 ab7 jtag_tck test clock i aa13 v14 ab6 jtag_rtck arm clock o aa12 w13 aa7 emulation jtag_tms_tmsc test mode select io aa18 v15 aa9 jtag_tdi test data input i aa20 u16 ab10 jtag_tdo test data output o aa19 y13 ab9 jtag_emu0 test emulation 0 io aa11 y15 ac24 jtag_emu1 test emulation 1 io aa10 y14 ad24 106 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-21. test interfaces C sdti signals description signal description [2] type [3] ball bottom ball bottom ball bottom subsystem name [1] (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] signal multiplexing [6] sdti_clk serial clock dual edge o af7 / aa11 / ag8 af6 / y15 / af9 ac9 / ac24 / ac11 etk_d11 / jtag_emu0 / etk_d14 sdti_txd0 serial data out (system trace o ag7 / aa10 / aa11 ae6 / y14 / y15 ac10 / ad24 / etk_d12 / jtag_emu1 / messages) ac24 jtag_emu0 sdti_txd1 serial data out (system trace o ah7 / aa10 af7 / y14 ad11 / ad24 etk_d13 / jtag_emu1 messages) sdti_txd2 serial data out (system trace o ag8 af9 ac11 etk_d14 messages) sdti_txd3 serial data out (system trace o ah8 ae9 ad12 etk_d15 messages) table 2-22. test interfaces C hwdbg signals description signal name [1] description [2] type [3] ball bottom ball bottom ball bottom (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] hw_dbg0 debug signal 0 o a24 / af10 c23/ab2 ac1/a22 hw_dbg1 debug signal 1 o a23 / ae10 d23/ab3 ad3/e18 hw_dbg2 debug signal 2 o c27/ af11 c26/ac3 ad6/j19 hw_dbg3 debug signal 3 o c23 / ag12 b23/ad4 ac6/h24 hw_dbg4 debug signal 4 o b24 / ah12 a24/ad3 ac7/g19 hw_dbg5 debug signal 5 o c24 / ae13 b24/aa3 ad8/f19 hw_dbg6 debug signal 6 o d24 / ae11 d24/y3 ac5/g20 hw_dbg7 debug signal 7 o a25 / ah9 c24/ab1 ad2/b21 hw_dbg8 debug signal 8 o b25 / af13 d25/ae3 ac8/f21 hw_dbg9 debug signal 9 o c26 / ah14 e26/ad2 ad9/g21 hw_dbg10 debug signal 10 o b23 / af9 a23/aa4 ac4/f18 hw_dbg11 debug signal 11 o d25 / ag9 d26/v2 ad5/j20 hw_dbg12 debug signal 12 o d28 / ae7 g25/ae4 ac3/g22 hw_dbg13 debug signal 13 o d26 / af7 k24/af6 ac9/e22 hw_dbg14 debug signal 14 o e26 / ag7 g26/ae6 ac10/d24 hw_dbg15 debug signal 15 o f28 / ah7 h25/af7 ad11/e23 hw_dbg16 debug signal 16 o f27 / ag8 h26/af9 ac11/e24 hw_dbg17 debug signal 17 o g26 / ah8 j26/ae9 ad12/f23 2.5.6 miscellaneous for more information, see timers / gp timers / gp timers environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-23. miscellaneous C gp timer signals description signal name [1] description [2] type [3] ball bottom ball bottom ball bottom (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] gpt_8_pwm_evt pwm or event for gp io n8 / ad25 / v3 c5 / ad21/ v9 g4/ m4 timer 8 gpt_9_pwm_evt pwm or event for gp io t8 / ab26 / y2 b4 / w8 / y24 f4 / n4 timer 9 gpt_10_pwm_evt pwm or event for gp io r8 / ab25 / y3 c4 / u8 / aa24 g5 / n3 timer 10 gpt_11_pwm_evt pwm or event for gp io p8 / aa25 / y4 b5 / v8 / ad22 f3 / m5 timer 11 copyright ? 2010 C 2011, texas instruments incorporated terminal description 107 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 2.5.7 general-purpose ios for more information, see general-purpose interface / general-purpose interface environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-24. general-purpose ios signals description (1) signal name [1] description [2] type [3] ball bottom ball bottom ball bottom (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] gpio_0 general-purpose io 0 io af26 v16 w16 gpio_1 general-purpose io 1 io af25 w15 y13 gpio_2 general-purpose io 2 io ah26 f3 ab12 gpio_3 general-purpose io 3 io ag26 d3 ac16 gpio_4 general-purpose io 4 io ae14 c3 ad17 gpio_5 general-purpose io 5 io af18 e3 ad18 gpio_6 general-purpose io 6 io af19 e4 ac17 gpio_7 general-purpose io 7 io ae21 g3 ab16 gpio_8 general-purpose io 8 io af21 d4 aa15 gpio_9 general-purpose io 9 io af22 v12 ad23 gpio_10 general-purpose io 10 io ag25 ae14 y7 gpio_11 general-purpose io 11 io aa11 y15 ac24 gpio_12 general-purpose io 12 io af10 ab2 ac1 gpio_13 general-purpose io 13 io ae10 ab3 ad3 gpio_14 general-purpose io 14 io af11 ac3 ad6 gpio_15 general-purpose io 15 io ag12 ad4 ac6 gpio_16 general-purpose io 16 io ah12 ad3 ac7 gpio_17 general-purpose io 17 io ae13 aa3 ad8 gpio_18 general-purpose io 18 io ae11 y3 ac5 gpio_19 general-purpose io 19 io ah9 ab1 ad2 gpio_20 general-purpose io 20 io af13 ae3 ac8 gpio_21 general-purpose io 21 io ah14 ad2 ad9 gpio_22 general-purpose io 22 io af9 aa4 ac4 gpio_23 general-purpose io 23 io ag9 v2 ad5 gpio_24 general-purpose io 24 io ae7 ae4 ac3 gpio_25 general-purpose io 25 io af7 af6 ac9 gpio_26 general-purpose io 26 io ag7 ae6 ac10 gpio_27 general-purpose io 27 io ah7 af7 ad11 gpio_28 general-purpose io 28 io ag8 af9 ac11 gpio_29 general-purpose io 29 io ah8 ae9 ad12 gpio_30 general-purpose io 30 io af24 ad7 y10 gpio_31 general-purpose io 31 io aa10 y14 ad24 gpio_34 general-purpose io 34 io n4 j2 k4 gpio_35 general-purpose io 35 io m4 h1 k3 gpio_36 general-purpose io 36 io l4 h2 k2 gpio_37 general-purpose io 37 io k4 g2 j4 gpio_38 general-purpose io 38 io t3 f1 j3 gpio_39 general-purpose io 39 io r3 f2 j2 gpio_40 general-purpose io 40 io n3 e1 j1 gpio_41 general-purpose io 41 io m3 e2 h1 gpio_42 general-purpose io 42 io l3 d1 h2 gpio_43 general-purpose io 43 io k3 d2 g2 gpio_44 general-purpose io 44 io h2 v1 r2 gpio_45 general-purpose io 45 io k2 y1 t2 gpio_46 general-purpose io 46 io p1 t1 u1 gpio_47 general-purpose io 47 io r1 u2 r3 108 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-24. general-purpose ios signals description (1) (continued) signal name [1] description [2] type [3] ball bottom ball bottom ball bottom (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] gpio_48 general-purpose io 48 io r2 u1 t3 gpio_49 general-purpose io 49 io t2 p1 u2 gpio_50 general-purpose io 50 io w1 l2 v1 gpio_51 general-purpose io 51 io y1 m2 v2 gpio_52 general-purpose io 52 io h3 ad1 na gpio_53 general-purpose io 53 io v8 a3 na gpio_54 general-purpose io 54 io u8 b6 d2 gpio_55 general-purpose io 55 io t8 b4 f4 gpio_56 general-purpose io 56 io r8 c4 g5 gpio_57 general-purpose io 57 io p8 b5 f3 gpio_58 general-purpose io 58 io n8 c5 g4 gpio_59 general-purpose io 59 io t4 n1 w2 gpio_60 general-purpose io 60 io g3 k2 k5 gpio_61 general-purpose io 61 io u3 j1 l1 gpio_62 general-purpose io 62 io h1 ac6 e1 gpio_63 general-purpose io 63 io l8 ac8 na gpio_64 general-purpose io 64 io k8 b3 na gpio_65 general-purpose io 65 io j8 c6 c2 gpio_66 general-purpose io 66 io d28 g25 g22 gpio_67 general-purpose io 67 io d26 k24 e22 gpio_68 general-purpose io 68 io d27 m25 f22 gpio_69 general-purpose io 69 io e27 f26 j21 gpio_70 general-purpose io 70 io ag22 ae21 ac19 gpio_71 general-purpose io 71 io ah22 ae22 ab19 gpio_72 general-purpose io 72 io ag23 ae23 ad20 gpio_73 general-purpose io 73 io ah23 ae24 ac20 gpio_74 general-purpose io 74 io ag24 ad23 ad21 gpio_75 general-purpose io 75 io ah24 ad24 ac21 gpio_76 general-purpose io 76 io e26 g26 d24 gpio_77 general-purpose io 77 io f28 h25 e23 gpio_78 general-purpose io 78 io f27 h26 e24 gpio_79 general-purpose io 79 io g26 j26 f23 gpio_80 general-purpose io 80 io ad28 ac26 ac22 gpio_81 general-purpose io 81 io ad27 ad26 ac23 gpio_82 general-purpose io 82 io ab28 aa25 ab22 gpio_83 general-purpose io 83 io ab27 y25 y22 gpio_84 general-purpose io 84 io aa28 aa26 w22 gpio_85 general-purpose io 85 io aa27 ab26 v22 gpio_86 general-purpose io 86 io g25 l25 j22 gpio_87 general-purpose io 87 io h27 l26 g23 gpio_88 general-purpose io 88 io h26 m24 g24 gpio_89 general-purpose io 89 io h25 m26 h23 gpio_90 general-purpose io 90 io e28 f25 d23 gpio_91 general-purpose io 91 io j26 n24 k22 gpio_92 general-purpose io 92 io ac27 ac25 v21 gpio_93 general-purpose io 93 io ac28 ab25 w21 gpio_94 general-purpose io 94 io a24 c23 a22 gpio_95 general-purpose io 95 io a23 d23 e18 gpio_96 general-purpose io 96 io c25 c25 b22 gpio_97 general-purpose io 97 io c27 c26 j19 gpio_98 general-purpose io 98 io c23 b23 h24 copyright ? 2010 C 2011, texas instruments incorporated terminal description 109 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-24. general-purpose ios signals description (1) (continued) signal name [1] description [2] type [3] ball bottom ball bottom ball bottom (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] gpio_99 general-purpose io 99 i ag17 ae16 ab18 gpio_100 general-purpose io 100 i ah17 ae15 ac18 gpio_101 general-purpose io 101 io b24 a24 g19 gpio_102 general-purpose io 102 io c24 b24 f19 gpio_103 general-purpose io 103 io d24 d24 g20 gpio_104 general-purpose io 104 io a25 c24 b21 gpio_105 general-purpose io 105 i k28 p25 l24 gpio_106 general-purpose io 106 i l28 p26 k24 gpio_107 general-purpose io 107 i k27 n25 j23 gpio_108 general-purpose io 108 i l27 n26 k23 gpio_109 general-purpose io 109 io b25 d25 f21 gpio_110 general-purpose io 110 io c26 e26 g21 gpio_111 general-purpose io 111 io b26 e25 c22 gpio_112 general-purpose io 112 i ag19 ad17 na gpio_113 general-purpose io 113 i ah19 ad16 na gpio_114 general-purpose io 114 i ag18 ae18 na gpio_115 general-purpose io 115 i ah18 ae17 na gpio_116 general-purpose io 116 io p21 u18 v20 gpio_117 general-purpose io 117 io n21 r18 t21 gpio_118 general-purpose io 118 io r21 t18 v19 gpio_119 general-purpose io 119 io m21 r19 r20 gpio_120 general-purpose io 120 io n28 (3) / t28 w19 / n19 (3) m23 (3) / r21 gpio_121 general-purpose io 121 io m27 (3) / t25 u20 / l18 (3) l23 (3) / r23 gpio_122 general-purpose io 122 io n27 (3) / r28 v19 / m19 (3) m22 (3) / p23 gpio_123 general-purpose io 123 io n26 (3) m18 (3) m21 (3) gpio_124 general-purpose io 124 io n25 (3) / t26 w18 / k18 (3) m20 (3) /r22 gpio_125 general-purpose io 125 io p28 (3) / t27 v20 / n20 (3) n23 (3) /t24 gpio_126 general-purpose io 126 io d25 / p27 (3) m20 (3) / d26 j20 / n22 (3) gpio_127 general-purpose io 127 io p26 (3) p17 (3) na gpio_128 general-purpose io 128 io r27 p18 na gpio_129 general-purpose io 129 io r25 (3) p19 (3) p24 (3) gpio_130 general-purpose io 130 io ae2 / u28 y20 / w10 y1 / t23 gpio_131 general-purpose io 131 io ag5 / u27 v18 / r10 ab5 / u24 gpio_132 general-purpose io 132 io ah5 t10 ab3 gpio_133 general-purpose io 133 io ah4 t9 y3 gpio_134 general-purpose io 134 io ag4 u10 w3 gpio_135 general-purpose io 135 io af4 u9 v3 gpio_136 general-purpose io 136 io ae4 v10 ab2 gpio_137 general-purpose io 137 io ah3 m3 aa2 gpio_138 general-purpose io 138 io af3 l3 y2 gpio_139 general-purpose io 139 io ae3 k3 aa1 gpio_140 general-purpose io 140 io af6 p3 v6 gpio_141 general-purpose io 141 io ae6 n3 v5 gpio_142 general-purpose io 142 io af5 u3 w4 gpio_143 general-purpose io 143 io ae5 w3 v4 gpio_144 general-purpose io 144 io ab26 y24 na gpio_145 general-purpose io 145 io ab25 aa24 na gpio_146 general-purpose io 146 io aa25 ad22 na gpio_147 general-purpose io 147 io ad25 ad21 na gpio_148 general-purpose io 148 io aa8 l4 w7 gpio_149 general-purpose io 149 io aa9 r2 w6 110 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-24. general-purpose ios signals description (1) (continued) signal name [1] description [2] type [3] ball bottom ball bottom ball bottom (cbp pkg.) [4] (cbc pkg.) [4] (cus pkg.) [4] gpio_150 general-purpose io 150 io w8 w2 ac2 gpio_151 general-purpose io 151 io y8 h3 v7 gpio_152 general-purpose io 152 io ae1 v3 na gpio_153 general-purpose io 153 io ad1 u4 na gpio_154 general-purpose io 154 io ad2 r3 na gpio_155 general-purpose io 155 io ac1 t3 na gpio_156 general-purpose io 156 io y21 u19 w19 gpio_157 general-purpose io 157 io aa21 v17 ab20 gpio_158 general-purpose io 158 io v21 u17 w18 gpio_159 general-purpose io 159 io u21 t20 y18 gpio_160 general-purpose io 160 io t21 t19 aa18 gpio_161 general-purpose io 161 io k26 p20 aa19 gpio_162 general-purpose io 162 io w21 t17 v18 gpio_163 general-purpose io 163 io h18 f23 a23 gpio_164 general-purpose io 164 io h19 f24 b23 gpio_165 general-purpose io 165 io h20 h24 b24 gpio_166 general-purpose io 166 io h21 g24 c23 gpio_167 general-purpose io 167 io b23 a23 f18 gpio_168 general-purpose io 168 io af15 c2 ac15 gpio_169 general-purpose io 169 io u26 w20 u23 gpio_170 general-purpose io 170 io j25 j23 a24 gpio_171 general-purpose io 171 io ab3 p9 t5 gpio_172 general-purpose io 172 io ab4 p8 r4 gpio_173 general-purpose io 173 io aa4 p7 t4 gpio_174 general-purpose io 174 io ac2 r7 t6 gpio_175 general-purpose io 175 io ac3 r8 na gpio_176 general-purpose io 176 io ab1 r9 na gpio_177 general-purpose io 177 io ab2 t8 r5 gpio_178 general-purpose io 178 io aa3 w7 n5 gpio_179 general-purpose io 179 io y2 w8 n4 gpio_180 general-purpose io 180 io y3 u8 n3 gpio_181 general-purpose io 181 io y4 v8 m5 gpio_182 general-purpose io 182 io v3 v9 m4 gpio_183 general-purpose io 183 io ae15 c1 ac14 gpio_184 general-purpose io 184 io af14 ab4 ac13 gpio_185 general-purpose io 185 io ag14 ac4 ac12 gpio_186 general-purpose io 186 io ae22 w11 aa6 gpio_188 general-purpose io 188 io u25 w17 w24 gpio_189 general-purpose io 189 io v28 y18 v23 gpio_190 general-purpose io 190 io v27 y19 w23 gpio_191 general-purpose io 191 io v26 y17 t22 (1) na in table stands for "not applicable". (2) the subsystem pin multiplexing options are not described in table 2-1 and table 2-4 . (3) the usage of this gpio is strongly restricted. for more information, see the general-purpose interface / general-purpose interface environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). copyright ? 2010 C 2011, texas instruments incorporated terminal description 111 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 2.5.8 power supplies note : for more information, see power reset and clock management / prcm environment and the power, reset, and clock management / prcm functional description / prcm voltage management functional description sections of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-25. power supplies signals description (1) signal name [1] description [2] ball bottom ball top ball bottom ball top ball bottom (cbp pkg.) [4] (cbp pkg.) (2) [5] (cbc pkg.) [4] (cbc pkg.) (2) [5] (cus pkg.) (2) [4] vdd_mpu_iva mpu/iva power y9 / w9 / t9 / na h7/ n7/ u7/ v7/ n8/ na w13/ w12/ v13/ supply r9 / m9 / l9 / j9 g9/ l9/ m9/ w9/ y9/ v12/ u13/ u12/ t8/ / y10 / u10 / t10 m10/ p10/ k11/ u11/ t7/ r8/ r7/ r6/ n8/ / r10 / n10 / v11/ y11/ g12/ d13/ n7/ n6/ m12/ m8/ m10 / l10 / j10 / u13 m7/ m6/ l12/ l11/ y11 / w11 / k11 j10/ j9/ h10/ h9/ / j11 / w12 / k13 g10/ g9/f10 / y14 / k14 / j14 / y15 / w15 / j15 vdd_core core power domain ac4 / j4 / h4 / na m7/ t7/ y8/ g11/ na t20/ t19/ t18/ t17/ d8 / ae9 / d9 / y12/ d15/ m17/ g18/ r19/ r18/ r17/ d15 / y16 / h20/ r20/ ac21 m15/ m14/ l15/ ae18 / y18 / l14/ k19/ k18/ k17/ w18 / k18 / j18 / j18/ j17/ h13/ h12/ ae19 / y19 / g13/ g12/ f13/ f12 u19 / t19 / n19 / m19 / j19 / y20 / w20 / v20 / u20 / p20 / n20 / k20 / j20 / d22 / d23 / ae24 / m25 / l25 / e25 cap_vddu_wkup_ decoupling aa15 na k14 na y12 logic capacitor for wkup/emu domains (logic) vdda_dplls_dll input power for the k15 na k13 na g18 analog part of the mpu, core dplls, iva, and the dll vdda_dac video dac power v25 na v25 na ab13 plane vssa_dac video dac ground y26 na v24 na ab15 plane vdds 1.8-v power for ad3 / ad4 / w4 / na g4/ m4/ t4/ y4/ l7/ a3 / a15 / b5 / f2 / y9 / w10 / w9 / v10 standard ios af8 / ae8 / ac7/ d9/ ae10/ c11/ f21/ l20 / w21 / v9 / u10 / n19 / af16 / ae16 / j15/ ac15/ a18/ j18/ n18 / n17 / m19 / af23 / ae23 / ac18/ ad20/ e24/ m18 / m17 f25 / f26 / ag27 l24/ t24/ w24/ ac24 / ab24 vdds_mem memory io power u1 / j1 / f1 / j2 / ac5 / p1 / h1 / f23 na na k8 / k7 / k6 / j8 / plane f2 / r4 / b5 / a5 / e1 / c23 / a4 / a7 j7 / j6 / h15 / g16 / / ah6 / b8 / a8 / / a10 / a15 / a18 g15 / f16 / f15 / b12 / a12 / d16 / e16 c16 / b18 / a18 / b22 / a22 / g28 / c28 vdda_dpll_per input power for the aa16 na u14 na u17 analog part of the peripheral dplls vdda_wkup_bg_bb for wakeup ldo aa14 na w14 na aa13 and vdda (2 ldos sram and bg) 112 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-25. power supplies signals description (1) (continued) signal name [1] description [2] ball bottom ball top ball bottom ball top ball bottom (cbp pkg.) [4] (cbp pkg.) (2) [5] (cbc pkg.) [4] (cbc pkg.) (2) [5] (cus pkg.) (2) [4] vss ground ag2 / u2 / b2 / h2 / b18 / ab5 / g1/ k1/ r1/ w1/ b2/ c1/ f1/ h2/ m2/ r2/ v16/ v15/ u16/ ag3 / w3 / p3 / ab14 / ab20 / p2 / h4/ n4/ r4/ w4/ ab5/ y6/aa7/ y11/ aa16/ u15/ u14/ u11/ j3 / e3 / a3 / p4 f22 / e2 / c22 / b4 / a6/ d7/ y7/ae7/ a8/ w20/p20/ l21/ h20/ u9/t16/ t15/ t14/ / e4 / ag6 / d7 / b7 / b10 / b15 g8/ d10/ g10/ l10/ f20/ b14/a13/ a7 t13/ t12/ t11/ t10/ c7 / v9 / u9 / p9 n10/ y10/ ac10/ t9/ r15/ r14/ r11/ / n9 / k9 / w10 / c12/ d12/a13/ d14/ r10/ p17/ p15/ p14/ v10 / p10 / k10 / ad14/ k15/ y16/ l17/ p13/p12/ p11/ p10/ d10 / c10 / n17/ r17/ d18/ p8/ n16/ n15/ n14/ af12 / ae12 / d20/g20/ e22/ ab22/ n13/ n12/ n11/ y12 / k12 / j12 / g23/ l23/ t23/ w23/ n10/ n9/ m16/ m13/ y13 / w13 / j13 / b25/ k25/u25/ ad25 / m11/ m10/ m9/ l17/ d13 / c13 / w14 y26 l13/ l10/ l8/ k15/ / k16 / j16 / w17 k14/ k11/ k10/ j16/ / k17 / j17 / w19 j15/ j14/ j13/ j12/ / v19 / r19 / p19 j11/h16/ h14/ h11 / l19 / k19 / d19 / c19 / af20 / ae20 / t20 / r20 / m20 / l20 / d21 / c22 / ac25 / y25 / w25 / ac26 / r26 / l26 / a26 / g27 / b27 vdds_sram sram ldos w16 na u12 na aa12 vdds_mmc1 input power for k25 na n23 na n24 mmc1 dual voltage buffers vdds_x power supply for p25 na p23 na h8 dual voltage gpios vss ground m28 na l19 na na vdd s io power plane ag20 na ad18 na na vss ground ag16 na ac16 na na vdd s io power plane h28 na l20 na na cap_vdd_sram_mpu_i decoupling v4 na n9 na u8 va capacitor for sram in processor domains cap_vdd_sram_core decoupling l21 na k20 na h17 capacitor for core domain (sram) vdd s io power plane ag21 na ad19 na na cap_vddu_array decoupling ah20 na ae19 na n20 capacitor for wkup/emu domains (array) vss ground ah21 na ac19 na na cap_vdd_bb_mpu_iva decoupling u4 na d6 na n21 capacitor for processor domains (bb) sys_xtalgnd kelvin ground y17 na af23 na w15 (1) na in this table stands for "not applicable". (2) for a list of pins not supported on a particular package, see table 2-4 . copyright ? 2010 C 2011, texas instruments incorporated terminal description 113 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 2.5.9 system and miscellaneous terminals note : for more information, see the power, reset, and clock management / prcm environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 2-26. system and miscellaneous signals description (1) signal name description [2] type [3] ball ball top ball ball top ball [1] bottom (cbp pkg.) bottom (cbc pkg.) bottom (cbp pkg.) (2) [5] (cbc pkg.) (2) [5] (cus pkg.) [4] [4] [4] sys_32k 32-khz clock input i ae25 na ae20 na aa16 sys_xtalin main input clock. oscillator input or lvcmos at ai-i ae17 na af19 na ad15 19.2, 13, or 12 mhz. sys_xtalout output of oscillator ao af17 na af20 na ad14 sys_altclk alternate clock source selectable for gptimers i j25 na j23 na a24 (maximum 54 mhz), usb (48 mhz), or ntsc/pal (54 mhz) sys_clkreq request from device for system clock (open io af25 na w15 na y13 source type) sys_clkout1 configurable output clock1 o ag25 na ae14 na y7 sys_clkout2 configurable output clock2 o ae22 na w11 na aa6 sys_boot0 boot configuration mode bit 0 i ah26 na f3 na ab12 sys_boot1 boot configuration mode bit 1 i ag26 na d3 na ac16 sys_boot2 boot configuration mode bit 2 i ae14 na c3 na ad17 sys_boot3 boot configuration mode bit 3 i af18 na e3 na ad18 sys_boot4 boot configuration mode bit 4 i af19 na e4 na ac17 sys_boot5 boot configuration mode bit 5 i ae21 na g3 na ab16 sys_boot6 boot configuration mode bit 6 i af21 na d4 na aa15 sys_nrespwron power on reset i ah25 na v13 na aa10 sys_nreswarm warm boot reset (open drain output) iod af24 na ad7 aa5 y10 sys_nirq external fiq input i af26 na v16 na w16 sys_nvmode1 indicates the voltage mode o ad26 na ad15 na y16 sys_nvmode2 indicates the voltage mode o ae26 na w16 na y15 sys_off_mode indicates the voltage mode o af22 na v12 na ad23 sys_ndmareq0 external a request 0 (system expansion). level i u8 na b6 na d2 (active low) or edge (falling) selectable. sys_ndmareq1 external a request 1 (system expansion). level i t8 / j8 na b4 / c6 na f4 / c2 (active low) or edge (falling) selectable. sys_ndmareq2 external a request 2 (system expansion). level i l3 / r8 na d1 / c4 na h2 / g5 (active low) or edge (falling) selectable. sys_ndmareq3 external a request 3 (system expansion). level i k3 / p8 na d2 / b5 na g2 / f3 (active low) or edge (falling) selectable. (1) na in this table stands for "not applicable". (2) for a list of pins not supported on a particular package, see table 2-4 . table 2-27. cbc package feed-through balls jedec 14x14mm, 0.65mm, jedec description (1) ball top ball bottom feed-through ball 152ball name nc no connect a1 a1 pop_a1_a1 d-vdd ddr supply j1 l1 pop_j1_l1 nc no connect aa1 af1 nc f-vdd flash supply n2 t2 pop_n2_t2 f-vdd flash supply t2 y2 pop_t2_y2 nc no connect w2 ae2 pop_w2_ae2 nc no connect y2 af4 pop_y2_af4 f-vdd flash supply aa6 af5 pop_aa6_af5 f-vdd flash supply y7 af8 pop_y7_af8 114 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 2-27. cbc package feed-through balls (continued) nc, int no connect; interrupt when y9 af10 pop_y9_af10 using onenand pop f-nbe0, cle0 no connect/cle aa10 af12 pop_aa10_af12 d-vdd ddr supply/ pop flash aa11 af13 pop_aa11_af13 vpp supply d-tq no connect/ ddr die aa12 af14 pop_aa12_af14 temperature sensor vss shared ground aa13 af15 pop_aa13_af15 d-vdd ddr supply y14 af17 pop_y14_af17 d-vddq ddr supply aa14 af16 pop_aa14_af16 d-vdd ddr supply b16 a20 pop_b16_a20 vss shared ground y17 af21 pop_y17_af21 d-vdd ddr supply aa17 af18 pop_aa17_af18 vss shared ground y19 af24 pop_y19_af24 d-vddq ddr supply aa19 af22 pop_aa19_af22 nc no connect a20 a25 pop_a20_a25 nc no connect y20 ae25 pop_y20_ae25 nc no connect aa20 af25 pop_aa20_af25 nc no connect a21 a26 pop_a21_a26 nc no connect b21 b26 pop_b21_b26 d-vdd ddr supply h21 k26 pop_h21_k26 d-vdd ddr supply p21 u26 pop_p21_u26 nc no connect y21 ae26 pop_y21_ae26 nc no connect aa21 af26 pop_aa21_af26 (1) for more details on the feedthrough pin connections, please refer to the pop memory datasheet. table 2-28. cbp package feed-through balls jedec 12x12, 0.5mm, jedec description (1) ball top ball bottom feed-through ball 168ball name d-vdd ddr supply a12 a15 pop_a12_a15 d-vdd ddr supply aa23 ae28 pop_aa23_ae28 d-vdd ddr supply h23 af28 pop_h23_af28 d-vdd ddr supply k1 j28 pop_k1_j28 d-vdd ddr supply y23 m1 pop_y23_m1 f-vdd flash supply aa1 aa1 pop_aa1_aa1 f-vdd flash supply ac8 af1 pop_ac8_af1 f-vdd flash supply ac13 ah10 pop_ac13_ah10 f-vdd flash supply l1 ah15 pop_l1_ah15 f-vdd flash supply u1 n1 pop_u1_n1 f-vpp flash vpp supply ac11 ah13 pop_ac11_ah13 nc, int0 no connect/pop onenand ab9 ag11 pop_ab9_ag11 interrupt nc, int1 no connect/pop onenand ac9 ah11 pop_ac9_ah11 interrupt nc no connect a1 a1 nc nc no connect a2 a2 nc nc no connect a22 a27 pop_a22_a27 nc no connect a23 a28 pop_a23_a28 nc no connect ab1 ag1 pop_ab1_ag1 nc no connect ab23 ag28 pop_ab23_ag28 nc no connect ac1 ah1 pop_ac1_ah1 nc no connect ac2 ah2 pop_ac2_ah2 nc no connect ac22 ah27 pop_ac22_ah27 nc no connect ac23 ah28 pop_ac23_ah28 copyright ? 2010 C 2011, texas instruments incorporated terminal description 115 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 2-28. cbp package feed-through balls (continued) nc no connect b1 b1 nc nc no connect b23 b28 pop_b23_b28 f-rst#, rp# flash reset ab11 ag13 pop_ab11_ag13 d-tq ddr temperature alert ac14 ah16 pop_ac14_ah16 vss shared ground aa2 aa2 pop_aa2_aa2 vss shared ground u2 af2 pop_u2_af2 vss shared ground aa22 af27 pop_aa22_af27 vss shared ground ab8 ag10 pop_ab8_ag10 vss shared ground ab13 ag15 pop_ab13_ag15 vss shared ground b12 b15 pop_b12_b15 vss shared ground h22 j27 pop_h22_j27 vss shared ground k2 m2 pop_k2_m2 vss shared ground k22 m26 pop_k22_m26 vss shared ground l2 n2 pop_l2_n2 (1) for more details on the feedthrough pin connections, please refer to the pop memory datasheet. 116 terminal description copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 3 electrical characteristics note for more information, see the power reset and clock management / prcm environment section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). 3.1 absolute maximum ratings stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under "recommended operating conditions" is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. table 3-1. absolute maximum rating over junction temperature range parameter min max unit vdd_mpu_iva supply voltage range for mpu / iva domain C 0.5 1.5 v vdd_core supply voltage range for core domain C 0.5 1.5 v vdda_wkup_bg_bb supply voltage range for wake-up domain (internal C 0.5 2.1 v ldo) vdda_dplls_dll supply voltage for mpu, iva, core dplls, and dll C 0.5 2.1 v vdda_dpll_per supply voltage for dplls (peripherals) C 0.5 2.1 v vdds_sram supply voltage for sram ldos C 0.5 2.1 v vdda_dac supply voltage for video buffers and dac C 0.5 2.1 v vdds supply voltage for 1.8-v i/o macros C 0.5 2.1 v vdds_mem supply voltage for memory buffers C 0.5 2.1 v vdds_mmc1 supply voltage range for mmc1 dual voltage ios C 0.5 3.8 v vdds _x supply voltage range for dual voltage gpios C 0.5 3.8 v jtag (9) 200 v esd esd stress hbm (human cam (6) 400 v voltage (1) body model) (2) gpmc (8) 500 other signals 1000 cdm (charged device model) (3) 250 i ioi current-pulse injection on each io pin (5) 200 ma i clamp clamp current for an input or output C 20 20 ma t stg (4) storage temperature range C 65 150 c (1) electrostatic discharge (esd) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. (2) level listed above is the passing level per ansi/esda/jedec js-001-2010. jedec document jep155 states that 500v hbm allows safe manufacturing with a standard esd control process, and manufacturing with less than 500v hbm is possible if necessary precautions are taken. pins listed as 1000v may actually have higher performance. (3) level listed above is the passing level per eia-jedec jesd22-c101e. jedec document jep157 states that 250v cdm allows safe manufacturing with a standard esd control process. pins listed as 250v may actually have higher performance. (4) for tape and reel the storage temperature range is [ C 10 c; +50 c] with a maximum relative humidity of 70%. it is recommended returning to ambient room temperature before usage. (5) each device is tested with an io pin injection of 200 ma with a stress voltage of 1.5 times the maximum vdd at room temperature. (6) corresponding signals: cam_d0, cam_d1, cam_d6, cam_d7, cam_d8, cam_d9. refer to multiplexing characteristics to determine the ball information per package. (7) corresponding signals: dss_data0, dss_data1, dss_data2, dss_data3, dss_data4, dss_data5. refer to multiplexing characteristics to determine the ball information per package. (8) corresponding signals: all 46 gpmc interface signals (vdds_mem is not included to this exception list). refer to multiplexing characteristics to determine the ball information per package. (9) corresponding signals: all 8 jtag interface signals (jtag_emu0, jtag_emu1, jtag_ntrst, jtag_rtck, jtag_tck, jtag_tdi, jtag_tdo, jtag_tms_tmsc). refer to multiplexing characteristics to determine the ball information per package. copyright ? 2010 C 2011, texas instruments incorporated electrical characteristics 117 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 3-2 summarizes the power consumption at the ball level. table 3-2. maximum current ratings at ball level (3) parameter max unit signal description vdd_mpu_iva (7) maximum current rating for mpu / iva processors dm3730/dm3725 (1g 1400 (1) (4) ma domain hz) dm3730/dm3725 (800m 1200 (5) hz) dm3730/dm3725 (600m 800 (5) hz) vdd_core (1) maximum current rating for core core dm3730 300 ma domain dm3725 230 vdds maximum current rating for 1.8-v i/o macros 60 ma vdds_mem maximum current rating for memory buffers 35 ma vdds_mmc1 (2) maximum current rating for mmc1 dual voltage buffers 20 ma vdds_x maximum current rating for gpio dual voltage buffers 2 ma vdda_wkup_bg_b maximum current rating for wake-up, bandgap and vbb ldos 5 ma b vdda_dac maximum current rating for video buffers and dac 60 ma vdda_dplls_dll maximum current rating for mpu, iva, core dplls and dll 30 ma vdda_dpll_per maximum current rating for dplls (peripherals) 10 ma vdds_sram maximum current rating for sram ldos (common) 41 ma (1) with smartreflex tm enabled. (2) mmc card and i/o card are not included. (3) the maximum current ratings documented in this table are preliminary data which are subject to change. (4) conditions used for maximum current ratings are worst case: C t j is up to 90c C cold process is used C v dd1 (vdd_mpu_iva) supplies 1.38 v (maximum voltage supported) in these conditions, the current listed as 1400mv is the addition of the: C current when running dhrystone on arm@1ghz multiplied by a factor x1.5 (to take care of neon activity) C current when running h.264 on iva@800mhz with a x1.1 factor (to take care of more aggressive sw than h.264) (5) conditions used for maximum current ratings are worst case: C t j is up to 90c C hot process is used C v dd1 (vdd_mpu_iva) nominal opp voltage: C dm3730 (800m hz): @1.27v C dm3730 (600m hz): @1.14v (6) this maximum vdd_mpu_iva current is observed at opp1g operating point. (7) depending on the microprocessor chosen, the iva feature may or may not be supported. see the features section for more information on device features. 118 electrical characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 3.2 recommended operating conditions the device is used under the recommended operating conditions described in table 3-4 . the poh information in table 3-3 is provided solely for your convenience and does not extend or modify the warranty provided under ti s standard terms and conditions for ti semiconductor products. table 3-3. reliability data junction temp total device lifetime opp130 max time opp1g max time @105c 89k poh not available not available @90c 100k poh 45k 25k (1) @75c > 100k poh 100k poh 75k (1) if device is only operated at opp1g, then poh can be extended to 35k poh. note logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. table 3-4. recommended operating conditions parameter description min nom max unit vdd_mpu_iva supply voltage range for arm / iva domain see (1) v maximum noise (peak-peak) 40 mv pp vdd_core supply voltage range for core domain see (1) v maximum noise (peak-peak) 40 mv pp vdds supply voltage for 1.8-v i/o macros 1.71 1.80 1.91 v maximum noise (peak-peak) oscillator io (crystal or 40 mv pp square modes) others 90 vdds_mem supply voltage for memory buffers 1.71 1.80 1.91 v maximum noise (peak-peak) 90 mv pp vdds_mmc1 supply voltage range for mmc1 1.8-v mode 1.71 1.80 1.91 v dual voltage ios 3.0-v mode 2.70 3.00 to 3.30 3.60 noise (peak-peak) 1.8-v mode 90 mv pp 3.0-v mode 150 vdds _x supply voltage range for x dual 1.8-v mode 1.71 1.80 1.91 v voltage ios 3.0-v mode 2.70 3.00 3.60 maximum noise (peak-peak) 1.8-v mode 90 mv pp 3.0-v mode 150 vdda_wkup_bg_ supply voltage range for wake-up ldo 1.71 1.80 1.91 v bb maximum noise (peak-peak) 50 mv pp vdda_dac analog supply voltage for video dac 1.71 1.80 1.91 v maximum noise (peak-peak) for a frequency from 0 to 100 30 mv pp khz (for a frequency > 100 khz, decreases 20 db/dec) vdds_sram supply voltage for sram ldos 1.71 1.80 1.91 v maximum noise (peak-peak) 50 mv pp vdda_dplls_dll supply voltage for mpu, iva, core dplls and dll 1.71 1.80 1.91 v maximum noise (peak-peak) 30 mv pp for any frequency copyright ? 2010 C 2011, texas instruments incorporated electrical characteristics 119 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 3-4. recommended operating conditions (continued) parameter description min nom max unit vdda_dpll_per supply voltage for dplls (peripherals) 1.71 1.80 1.91 v maximum noise (peak-peak) 50 mv pp for any frequency vssa_dac ground for video buffers and dac 0 v vss main ground 0 v t j operating junction temperature commercial 0 90 c range temperature industrial temperature -40 90 extended temperature -40 105 (1) see section 4.3.4 , processor clocks . opp voltage values may change following the silicon characterization result. 120 electrical characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 3.3 dc electrical characteristics table 3-5 summarizes the dc electrical characteristics. note: the interfaces or signals described in table 3-5 correspond to the interfaces or signals available in multiplexing mode 0. all interfaces or signals multiplexed on the balls / pins described in table 3-5 have the same dc electrical characteristics. table 3-5. dc electrical characteristics parameter min nom max unit sdrc mode (cbp balls (19) : c14 / b14 / c15 / b16 / d17 / c17 / b17 / d18 / h9 / h10 / h11 / h12 / a13 / a14 / h16 / h17 / h14 / h13 / h15 / a16 / a17) (4) v ih high-level input voltage 0.7 * vdds_mem v v il low-level input voltage 0.3 * vdds_mem v v hys (1) hysteresis voltage at an input 0.07 v v oh high-level output voltage, driver enabled, i oh = C 4 ma 0.8 * vdds_mem vdds_mem v pullup or pulldown disabled v ol low-level output voltage, driver enabled, i ol = 4 ma 0 0.2 * vdds_mem v pullup or pulldown disabled c in input capacitance 1.15 pf t tin (2) input recommended rise, t rin , and fall time, t fin (measured 10 ns between 20% and 80% at pad) t rout (2) output maximum rise time (rise time, t rout , evaluated 1.15 ns between 20% and 80% at pad) @ maximum load t fout (2) output maximum fall time (fall time, t fout , evaluated 1.10 ns between 20% and 80% at pad) @ maximum load c out load capacitance ds0 = 0 (3) 2 4 pf ds0 = 1 (3) 4 12 mmc interface 1 mode (cbp balls (19) : n28 / m27 / n27 / n26 / n25 / p28) 1.8-v mode v ih high-level input voltage 0.70 * vdds_mmc1 vdds_mmc1 + 0.3 v v il low-level input voltage C 0.3 0.30 * vdds_mmc1 v v oh high-level output voltage with 100- a sink current i oh vdds_mmc1 C 0.2 v v ol low-level output voltage with 100- a sink current at 0.2 v vdds_mmc1 minimum v hys (1) hysteresis voltage at an input 0.1 v t tin (2) input transition time (t rin or t fin evaluated normal mode 3 ns between 10% and 90% at pad) (speedctrl = 1) (4) high-speed 8 (speedctrl = 0) (4) c out load capacitance 10 30 pf l out line inductance (except vdds_mmc1) 16 nh 3.0-v mode v ih high-level input voltage 0.625 * vdds_mmc1 vdds_mmc1 + 0.3 v v il low-level input voltage C 0.3 0.25 * vdds_mmc1 v v oh high-level output voltage with 100- a sink current i oh 0.75 * vdds_mmc1 v v ol low-level output voltage with 100- a source current at 0.125 * vdds_mmc1 v vdds_mmc1 minimum v hys (1) hysteresis voltage at an input 0.05 v copyright ? 2010 C 2011, texas instruments incorporated electrical characteristics 121 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 3-5. dc electrical characteristics (continued) parameter min nom max unit t tin (2) input transition time (t rin or t fin evaluated normal mode 3 ns between 10% and 90% at pad) (speedctrl = 1) (4) high-speed 8 (speedctrl = 0) (4) c out load capacitance 10 30 pf l out line inductance (except vdds_mmc1) 16 nh gpio mode (cbp balls (19) : p27 / p26 / r25) 1.8-v mode v ih high-level input voltage 0.70 * vdds_ x vdds_ x + 0.3 v v il low-level input voltage C 0.3 0.20 * vdds_ x v v oh high-level output voltage with 20- a sink current i oh 0.8 * vdds_ x vdds_ x + 0.3 v v ol low-level output voltage with 1-ma source current at vdds_ x C 0.3 0.4 v minimum v hys (1) hysteresis voltage at an input 0.1 v t tin (2) input transition time (t rin or t fin evaluated normal mode 35 ns between 10% and 90% at pad) (speedctrl = 1) (4) c in input capacitance 2.5 pf c out load capacitance 30 pf l out line inductance (except vdds_ x) 16 nh 3.0-v mode v ih high-level input voltage 0.70 * vdds_ x vdds_ x + 0.3 v v il low-level input voltage C 0.3 0.20 * vdds_ x v v oh high-level output voltage with 20- a sink current i oh 0.7 * vdds_ x vdds_ x + 0.3 v v ol low-level output voltage with 1-ma source current at C 0.3 0.4 v vdds_sim minimum v hys (1) hysteresis voltage at an input 0.05 v t tin (2) input transition time (t rin or t fin evaluated normal mode 35 ns between 10% and 90% at pad) (speedctrl = 1) (4) c in input capacitance 2.5 pf c out load capacitance 30 pf l out line inductance (except vdds_ x) 16 nh i 2 c mode (cbp balls (19) : k21 / j21 / af15 / ae15 / af14 / ag14 / ad26 / ae26) (6) standard mode v ih high-level input voltage 0.7 * vdds vdds + 0.5 v v il low-level input voltage C 0.5 0.3 * vdds v v hys (1) hysteresis voltage at an input 0.15 v v ol low-level output voltage open-drain at 3-ma sink current na (18) na (18) v i i input current at each i/o pin with an input voltage between C 10 10 a 0.1 * vdds to 0.9 * vdds c i capacitance for each i/o pin 10 pf t fout (5) output fall time from v ihmin to v ilmax with a bus capacitance 250 ns c b from 10 pf to 400 pf t rout (5) output rise time with a capacitive load from 10 pf to 150 pf 20 + 0.1c b 250 ns with internal pullup fast mode v ih high-level input voltage 0.7 * vdds vdds + 0.5 v v il low-level input voltage C 0.5 0.3 * vdds v 122 electrical characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 3-5. dc electrical characteristics (continued) parameter min nom max unit v hys (1) hysteresis voltage at an input 0.15 v v ol low-level output voltage open-drain at 3-ma sink current 0 0.2 * vdds v i i input current at each i/o pin with an input voltage between C 10 10 a 0.1 * vdds to 0.9 * vdds c i capacitance for each i/o pin 10 pf t fout (5) output fall time from v ihmin to v ilmax with a bus capacitance 20 + 0.1c b 250 ns c b from 10 pf to 400 pf t rout (5) output rise time with a capacitive load from 10 pf to 150 pf 20 + 0.1c b 250 ns with internal pullup high-speed mode v ih high-level input voltage 0.7 * vdds vdds + 0.5 v v il low-level input voltage C 0.5 0.3 * vdds v v hys (1) hysteresis voltage at an input 0.15 v v ol low-level output voltage open-drain at 3-ma sink current 0 0.2 * vdds v i i input current at each i/o pin with an input voltage between C 10 10 a 0.1 * vdds to 0.9 * vdds c i capacitance for each i/o pin 10 pf t fout (5) (6) output fall time with a capacitive load from 10 pf to 100 pf 10 40 ns at 3-ma sink current output fall time with a capacitive load of 400 pf at 3-ma 20 80 ns sink current t rout (5) output rise time with a capacitive load from 10 pf to 80 pf 10 40 ns with internal pullup standard lvcmos mode v ih high-level input voltage 0.7 * vdds vdds v v il low-level input voltage C 0.5 0.3 * vdds v v oh high-level output voltage at 4-ma sink current vdds C 0.45 v v ol low-level output voltage at 4-ma sink current 0.45 v c in input capacitance 1.15 pf t tin (2) input transition time (t rin or t fin evaluated between 10% and 10 ns 90% at pad) t tout output transition time at 40-pf load (t rout or t fout 10 ns evaluated between 10% and 90% at pad) mipi d-phy interface mipi d-phy interface - gpi mode (cbp balls (19) : ag19 / ah19 / ag18 / ah18 / k28 / l28 / k27 / ag17 / ah17) v ih (7) high-level input voltage 0.65 * vdds_x (14) vdds_x + 0.3 (14) v v il (8) low-level input voltage C 0.3 0.35 * vdds_x (14) v v hys (1) hysteresis voltage at an input 0.15 v c in input capacitance 1.3 pf t tin (2) input transition time (t rin or t fin evaluated between 10% and 10 ns 90% at pad) other balls common to "other balls" v ih high-level input voltage 0.65 * vdds vdds + 0.3 v v il low-level input voltage C 0.3 0.35 * vdds v v hys (1) hysteresis voltage at an input 0.15 v v oh high-level output voltage, driver enabled, i oh = C x (17) vdds C 0.45 v pullup or pulldown disabled ma v ol low-level output voltage, driver enabled, i ol = x (17) ma 0.45 v pullup or pulldown disabled differences between "other balls" copyright ? 2010 C 2011, texas instruments incorporated electrical characteristics 123 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 3-5. dc electrical characteristics (continued) parameter min nom max unit input capacitance and input transition time sys_xtalin pin (cbp ball (19) : ae17) c in input capacitance 1.00 1.15 1.35 pf t tin (2) input transition time (rise time, t rin or fall time, t fin 10 ns evaluated between 10% and 90% at pad) jtag interface (cbp balls (19) : aa17 / aa13 / aa12 / aa18 / aa20 / aa19 / aa11 / aa10) c in input capacitance 2.20 pf t tin (2) input transition time (rise time, t rin or fall time, t fin 10 ns evaluated between 10% and 90% at pad) otherwise c in input capacitance 1.15 pf t tin (2) input transition time (rise time, t rin or fall time, t fin 10 ns evaluated between 10% and 90% at pad) output capacitance load and output transition time sys_32k, sys_clkreq, sys_off_mode, sys_clkout1, sys_nirq, uart3_cts_rctx, uart3_rts_sd, uart3_rx_irrx, uart3_tx_irtx, hdq_sio (cbp balls (19) : r27 / ae25 / af25 / af22 / ag25 / af26 / h18 / h19 / h20 / h21 / j25) t tout output transition time (rise time, t rout or ds[1:0] = 00 (3) 1 (15) 15 (16) ns fall time, t fout evaluated between 10% and 90% at pad) c tout output load 4 60 pf t tout output transition time (rise time, t rout or ds[1:0] = 10 (3) 0.4 (15) 5 (16) ns fall time, t fout evaluated between 10% and 90% at pad) c tout output load 2 21 pf t tout output transition time (rise time, t rout or ds[1:0] = 01 (3) 0.6 (15) 7 (16) ns fall time, t fout evaluated between 10% and 90% at pad) c tout output load 7 33 pf cam, hsusb0, mmc2, uart1, uart2, mcbsp, mcspi, etk interfaces, sys_clkout2 (cbp ball (19) : ae22) t tout output transition time (rise time, t rout or fall time, t fout 1.5 5 ns evaluated between 10% and 90% at pad) c tout output load 2 22 pf otherwise t tout output transition time (rise time, t rout or fall time, t fout 0.6 2.4 (17) ns evaluated between 10% and 90% at pad) c tout output load 2 22 pf hysteresis sys_xtalin pin (cbp ball (19) : ae17) v hys (1) hysteresis voltage at an input 0.25 v hsusb0_clk (cbp ball (19) : t28) v hys (1) hysteresis voltage at an input 0.07 v otherwise v hys (1) hysteresis voltage at an input 0.15 v (1) v hys is the magnitude of the difference between the positive-going threshold voltage v t+ and the negative-going threshold voltage v t C . some receivers, but not all, are designed for hysteresis. v hys applies only to those that are. (2) the t in (t rin and t fin also) value is the recommended condition. the t in (t rin and t fin also) mismatch causes additional delay time inside the device then leads to ac timing invalidation in this dm. the t in (t rin and t fin also) mismatch does not necessarily mean functional failure. this global value may be overridden on a per interface basis if another value is explicitly defined for that interface in the timing requirements and switching characteristics chapter of the data manual. (3) for a full description of the ds0 load compensation register configuration, see the description of the control_prog_io1 configuration registers in system control module / programming model / feature settings / sdrc i/o drive strength selection section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). 124 electrical characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (4) for a full description of the speedctrl speed register configuration, see the description of the control_prog_io1 configuration registers in system control module / programming model / feature settings section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (5) rise and fall times are specified for (0.3 * vdds) to (0.7 * vdds). (6) for capacitive load from 100 pf to 400 pf, fall time should be linearly interpolated: t fmin = (1 + (load C 100 pf) / 300 pf) * 10 ns t fmax = (1 + (load C 100 pf) / 300 pf) * 40 ns (7) v ih is the voltage at which the receiver is required to detect a high state in the input signal. (8) v il is the voltage at which the receiver is required to detect a low state in the input signal. v il is larger than the maximum single-ended line voltage during hs transmission. therefore, both lp receivers will detect low during hs signaling. (9) this value includes a ground difference of 50 mv between the transmitter and the receiver, the status common-mode level tolerance and variations below 450 mhz. (10) common mode is defined as the average voltage level of dx and dy: v cm = (v (dx) + v (dy) )/2. common mode ripple may be due to rise-fall time and transmission line impairments in the pcb. (11) value when driving into differential load impedance anywhere in the range 80 to 125 ? . (12) ulpm stands for ultra low power mode. (13) ui = 1 / (2 * fh), where fh is the fundamental frequency of hs data transmission. for example, for 800 mbps fh is 400 mhz. (14) vdda_x can be vdda_csiphy1 or vdda_csiphy2 depending on the interface used. (15) at minimum load. (16) at maximum load. caution: this creates emi parasitics up to 1.2 ns. (17) for more information about ioh / iol values, see one of the tables in the ball characteristics section, column buffer drive strength (ma) . (18) no v ol specifications are applicable in standard mode. (19) for associated cbc and cus balls, please refer to the section 2.4 , multiplexing characteristics table. copyright ? 2010 C 2011, texas instruments incorporated electrical characteristics 125 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 3.4 external capacitors to improve module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. a decoupling capacitor is most effective when it is close to the device, because this minimizes the inductance of the circuit board wiring and interconnects. 3.4.1 voltage decoupling capacitors table 3-6 summarizes the core voltage decoupling characteristics. 3.4.1.1 core voltage decoupling capacitors to improve module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. a decoupling capacitor is most effective when it is close to the device, because this minimizes the inductance of the circuit board wiring and interconnects. table 3-6. core voltage decoupling characteristics parameter min typ max unit c vdd_core (1) 0.6 1.2 1.8 f c vdd_mpu_iva (2) see (2) f (1) the typical value corresponds to 2 capacitors of 470 nf, plus 3 capacitors of 100 nf. except for the decoupling capacitance values, the pcb rules of the pcb design requirements for vdd_mpu_iva power distribution network for ti omap3630, am37xx, and dm37xx microprocessors (sprabj7) application note can be used. (2) for more information regarding the vdd_mpu_iva decoupling capacitance recommendations, see the pcb design requirements for vdd_mpu_iva power distribution network for ti omap3630, am37xx, and dm37xx microprocessors (sprabj7) application note. 3.4.1.2 io and analog voltage decoupling capacitors table 3-7 summarizes the power supply decoupling capacitor characteristics. table 3-7. power supply decoupling capacitor characteristics parameter min typ max unit c vdds (1) (2) 200 400 600 nf c vdds_mem (1) (3) 350 700 1050 nf c vdds_mmc1 (4) 50 100 150 nf c vdds_x (4) 50 100 150 nf c vdda_dplls_dll (4) 50 100 150 nf c vdda_dpll_per (4) 50 100 150 nf c vdds_sram (4) 110 220 330 nf c vdda_wkup_bg_bb (4) 240 470 700 nf c vdda_dac (4) 50 100 150 nf (1) in power plan configuration. (2) the typical value corresponds to 4 capacitors of 100 nf. (3) the typical value corresponds to 7 capacitors of 100 nf. (4) in power rail configuration. 126 electrical characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 3.4.2 output capacitors the capacitors at the outputs are required to stabilize the internal ldo supply voltages. the capacitors must be placed as close as possible to the balls. table 3-8 summarizes the power supply decoupling characteristics. table 3-8. output capacitor characteristics parameter min typ max unit c cap_vdd_sram_mpu_iva 0.7 1 1.3 f c cap_vdd_sram_core 0.7 1 1.3 f c cap_vddu_wkup_logic 0.7 1 1.3 f c cap_vddu_array 0.7 1 1.3 f c cap_vdd_bb_mpu_iva 0.7 1 1.3 f copyright ? 2010 C 2011, texas instruments incorporated electrical characteristics 127 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 3-1 illustrates an example of the external capacitors. figure 3-1. external capacitors 128 electrical characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 cap_vdd_sram_mpu_iva cap_vdd_sram_core vdds_sram dpll5 dpll4 vdda_dpll_per mmc i/os vdds_mmc1 vss vssa_dac cvdds_sram ccap_vdd_sram_mpu_iva ccap_vdd_sram_core cvdda_dplls_dll cvdda_dpll_per cvdds_mmc1 vdda_dac vdds_mmc1 vdds_sram vdda_dpll_per vdda_dplls_dll vdds_mem cvdds_mem core vdd_core cvdd_core vdd_core vdda_wkup_bg_bb vdda_wkup_bg_bb cap_vddu_wkup_logic cvdda_wkup_bg_bb ccap_vddu_array cap_vddu_array dll dpll_mpu dpll_iva dpll_core vdda_dplls_dll wkup_logic bg sram_ldo1 sram_ldo2 video dac vdds_mem mpu vdd_mpu_iva vdd_mpu_iva cvdd_mpu_iva vdds vdds i/o cvdda_dac vdds_mem cvdds vdds bbldo cap_vdd_bb_mpu_iva ccap_vddu_wkup_logic oscillator device vdda_dac ccap_vdd_bb_mpu_iva
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 note ? decoupling capacitors must be placed as closed as possible of the power ball. choose the ground located closest to the power pin for each decoupling capacitor. in case of interconnecting powers, first insert the decoupling capacitor and then interconnect the powers. ? the decoupling capacitor value depends on the board characteristics. 3.5 power-up and power-down sequences this section provides the timing requirements for the device hardware signals. note ? if the mmc dual voltages interfaces are used with 1.8-v or 3.0-v, then the power-up and power-down sequences specified in the figure 3-2 and figure 3-3 must be followed carefully to avoid any significant current consumption. ? if the mmc dual voltages interfaces are used with 1.8-v only (3.0-v is never used), then vdds_mmc1, vdds_x may be connected to the main power supply vdds so that they ramp up together before vdd_core. 3.5.1 power-up sequence note for more information, see the power, reset, and clock management / prcm functional description / prcm reset manager functional description / reset sequences of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). figure 3-2 shows the power-up sequence. copyright ? 2010 C 2011, texas instruments incorporated electrical characteristics 129 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) 1.2 v supported. (2) if an external square clock is provided, it could be started after sys_nrespwron release, provided it is clean, i.e. no glitch, stable frequency and duty cycle. (3) sys_32k can be turned on any time between the vdds ramp-up and the sys_nrespwron release. figure 3-2. power-up sequence 3.5.2 power-down sequence the following steps give two examples of power-down sequence supported by the dm37x device. 1. put the dm37x device under reset (sys_nrespwron) 2. stop all signals driven to its balls (sys_32k, sys_xtalin) 3. either: ( a) shutdown all power domains at once. this sequence is described in black color in figure 3-3 . ( b) or, if the shutdown is sequenced, you must follow these steps (described in dash style blue color in figure 3-3 ): C turn off all complex io domains (vdds_mmc1, vdds_x) C turn off all the core and mpu domains (vdd_core, vdd_mpu_iva) C turn off all dpll domains (vdda_dplls_dll, vdda_dpll_per) C turn off all sram ldos (vdds_sram) C turn off all reference domains (vdda_wkup_bg_bb) C turn off all standard io domains (vdds, vdds_mem) figure 3-3 shows both power-down sequences: one of them is described in black color, and the other one in dash style blue. 130 electrical characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 vdds, vdds_mem, vdds_sram, vdda_wkup_bg_bb vdda_dplls_dll, vdda_dpll_per vdd_core vdd_mpu_iva sys_32k sys_xtalin sys_nrespwron sys_nreswarm vdds_mmc1, vdds_x, vdda_dac 1.8 v 1.1 v (1) 1.1 v (1) 1.8 v
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 a. sys_32k can be turned off any time between the sys_nrespwron assertion and the vdds shut down. figure 3-3. power-down sequence alternate power-down sequence : ? vdd_mpu_iva shuts down before vdd_core. ? vdda_sram, vdda_wkup_bg_bb, vdds and vdds_mem shut down simultaneously. ? vdda_dplls_dll and vdda_dpll_per shut down anytime between all complex io domains shut down and vdda_sram shuts down. copyright ? 2010 C 2011, texas instruments incorporated electrical characteristics 131 submit documentation feedback product folder link(s): dm3730 dm3725 vdda_dplls_dll, vdda_dpll_per vdd_core vdd_mpu_iva sys_32k sys_xtalin sys_nrespwron vdds_mmc1, vdds_x, vdda_dac vdds_sram vdda_wkup_bg_bb vdds, vdds_mem
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 4 clock specifications note for more information, see the power, reset, and clock management / prcm environment / external clock signal and power, reset and clock management / prcm functional description / prcm clock manager functional description sections of the am/dm37x multimedia device technical reference manual ( sprugn4 ). figure 4-1 shows external input clock sources and output clocks. figure 4-1. clock interface 132 clock specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 device sys_32k sys_altclk sys_clkout1 alternate clock source selectable (48-mhz, 54-mhz) to quartz (oscillator output) or unconnected from quartz (oscillator input) or square clock clock request. to square clock source or from peripherals oscillator is used oscillator is bypassed unconnected square clock source to peripherals (from oscillator clock [sys_xtalin]): 12-,13-, 16.8-, 19.2-, 26-, or 38.4-mhz or core_clk: up to 332 mhz (possible divider: 4, 8, 16) or dpll 54-mhz, dpll 96-mhz (possible divider: 1, 2, 4, 8, or 16) gpin to peripherals (from oscillator clock [sys_xtalin]): 12-,13-, 16.8-, 19.2-, 26-, or 38.4-mhz (no divider) sys_clkout2 sys_xtalout sys_xtalin sys_clkreq sys_xtalout sys_xtalin sys_clkreq sys_xtalout sys_xtalin sys_clkreq from power ic: 32 768-hz swps038-006
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 the device operation requires the following three input clocks: ? the sys_32k 32-khz clock is used for low frequency operation. it supplies the wake-up domain for operation in lowest power mode (off mode). this clock is provided through the sys_32k pin. ? the sys_altclk system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 mhz or 54 mhz. ? the sys_xtalin / sys_xtalout system input clock (12, 13, 16.8, 19.2, 26, or 38.4 mhz) is used to generate the main source clock of the device. it supplies the dplls as well as several other modules. the system input clock can be connected to either: C a crystal oscillator clock managed by sys_xtalin and sys_xtalout. in this case, the sys_clkreq is used as an input (gpin). C a cmos digital clock through the sys_xtalin pin. in this case, the sys_clkreq is used as an output to request the external system clock. the device outputs externally two clocks: ? sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 mhz) at any time. it can be controlled by software or externally using sys_clkreq control. when the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. the off state polarity of sys_clkout1 is programmable. ? sys_clkout2 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 mhz), core_clk (core dpll output), 96 mhz or 54 mhz. it can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. this output is active only when the core power domain is active. 4.1 input clock specifications 4.1.1 input clock requirements table 4-1 illustrates the requirements to supply a clock to the device. table 4-1. input clock requirements (4) pad clock frequency stability duty cycle jitter transition sys_32k 32.768 khz +/- 200 ppm - - < 10 ns sys_xtalout 12, 13, 16.8, or 19.2 mhz crystal 50 ppm ( 5 - - - sys_xtalin ppm) (1) 12, 13, 16.8, 19.2, 26, or 38.4 mhz square 50 ppm ( 5 45% to 55% x% (2) * 10 ns ppm) (1) tc(xtalin) (3) - 200ps sys_altclk 48 or 54 mhz +/-50 ppm 49% to 51% < 1% 10 ns (1) 50 ppm is the clock frequency stability/accuracy and 5 ppm takes into account the aging effects. (2) depending on the internal system clock divider configuration (prcm.prm_clksrc_ctrl[7:6], sysclkdiv bit field), the sys_xtalin input clock can be divided by 2 to provide the standard system clock (sys_clk) frequencies. for more information, see the power, reset, and clock management chapter of the am/dm37x multimedia device technical reference manual ( sprugn4 ). in x%, x represents then the internal system clock divider with following possible values: x = 1 or 2. (3) tc(xtalin) is the sys_xtalin cycle time of the clock coming to sys_xtalin ball. (4) in this table, the transition times are calculated for 10%-90% of vdds. for more information on the corresponding vdds power supply name, please see the ball characteristics table corresponding to your package. the power column defines the vdds power supply for each ball. copyright ? 2010 C 2011, texas instruments incorporated clock specifications 133 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 4.1.2 sys_xtalin / sys_xtalout external crystal an external crystal is connected to the device pins. figure 4-2 describes the crystal implementation. figure 4-2. crystal implementation 1. when the crystal oscillator is in bypass mode (crystal implementation is unused), the sys_xtalgnd ball is not connected. the crystal must be in the fundamental mode of operation and parallel resonant. table 4-2 summarizes the required electrical constraints. table 4-2. crystal electrical characteristics (1) name description min typ max unit f p parallel resonance crystal frequency (1) 12, 13, 16.8, or 19.2 mhz c f1 c f1 load capacitance for crystal parallel resonance with c f1 = c f2 12 24 pf c f2 c f2 load capacitance for crystal parallel resonance with c f1 = c f2 12 24 pf esr(c f1 ,c f2 ) (2) frequency 12 mhz , negative resistor at nominal 500 ? , negative 100 ? resistor at worst case 300 ? frequency 13 mhz, negative resistor at nominal 400 ? , negative 80 ? resistor at worst case 240 ? frequency 16.8 mhz and 19.2 mhz, negative resistor at nominal 60 ? 300 ? , negative resistor at worst case 180 ? c o crystal shunt capacitance 4.5 pf dl crystal drive level 0.5 mw (1) measured with the load capacitance specified by the crystal manufacturer. this load is defined by the foot capacitances tied in series. if c l = 20 pf, then both foot capacitors will be c f1 = c f2 = 40 pf. parasitic capacitance from package and board must also be taken in account. (2) the crystal motional resistance r m is related to the equivalent series resistance (esr) by the following formula: esr = r m * (1 + (c o * c f1 * c f2 / (c f1 + c f2 ))) 2 . when selecting a crystal, the system design must take into account the temperature and aging characteristics of a crystal versus the user environment and expected lifetime of the system. 134 clock specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 device sys_xtalin sys_xtalgnd sys_xtalout cf1 cf2 crystal
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 4-3 details the switching characteristics of the oscillator and the requirements of the input clock. table 4-3. oscillator switching characteristics crystal mode name description min typ max unit f p oscillation frequency 12, 13, 16.8, or 19.2 mhz t sx start-up time (1) (2) 3 ms (1) start-up time is defined as the time the oscillator takes to gain sys_xtalin amplitude enough to have 45% to 55% duty cycle at the core input from the time power down (pwrdn) is released. start-up time is a strong function of crystal parameters. at power-on reset, the time is adjustable using the pin itself. the reset must be released when the oscillator or clock source is stable. to switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 s; however, if the chip comes from bypass mode to crystal mode then the crystal will start-up after time mentioned in the t sx parameter. (2) before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in application mode and receives a square wave. the switching time in this case is about 100 s. 4.1.3 sys_xtalin squarer input clock table 4-4 summarizes the base oscillator electrical characteristics. table 4-4. oscillator electrical characteristics bypass mode name description min typ max unit f frequency 12, 13, 16.8, 19.2, 26, or 38.4 mhz c i input capacitance 1.00 1.15 1.35 pf r i input resistance 160 216 280 ? t sx start-up time (1) see (2) ms (1) to switch from bypass mode to crystal mode or from crystal mode to bypass mode, there is a waiting time about 100 s; however, if the chip comes from bypass mode to crystal mode then the crystal will start-up after time mentioned in table 4-3 , t sx parameter above. (2) before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in application mode and receives a square wave. the switching time in this case is about 100 s. copyright ? 2010 C 2011, texas instruments incorporated clock specifications 135 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 4-5 details the squarer input clock timing requirements. table 4-5. sys_xtalin squarer input clock timing requirements bypass mode (5) name description min typ max unit ocs0 1 / t c(xtalin) frequency, sys_xtalin 12, 13, 16.8, 19.2, 26, or 38.4 mhz ocs1 t w(xtalin) pulse duration, sys_xtalin low or high 0.45 * t c(xtalin) 0.55 * t c(xtalin) ns t j(xtalin) peak-to-peak jitter (1) , sys_xtalin x% (2) * ps tc(xtalin) (3) - 200 t r(xtalin) rise time, sys_xtalin 10 ns t f(xtalin) fall time, sys_xtalin 10 ns t j(xtalin) frequency stability, sys_xtalin +/-50 ppm (+/-5ppm) (4) (1) C peak-to-peak jitter is meant here as follows: C the maximum value is the difference between the longest measured clock period and the expected clock period C the minimum value is the difference between the shortest measured clock period and the expected clock period maximum and minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock period (2) depending on the internal system clock divider configuration (prcm.prm_clksrc_ctrl[7:6], sysclkdiv bit field), the sys_xtalin input clock can be divided by 2 to provide the standard system clock (sys_clk) frequencies. for more information, see the power, reset, and clock management chapter of the am/dm37x multimedia device technical reference manual ( sprugn4 ). in x%, x represents then the internal system clock divider with following possible values: x = 1 or 2. (3) tc(xtalin) is the sys_xtalin cycle time of the clock coming to sys_xtalin ball. (4) 50 ppm is the clock frequency stability/accuracy and 5 ppm takes into account the aging effects. (5) in this table, the transition times are calculated for 10%-90% of vdds. for more information on the corresponding vdds power supply name, please see the ball characteristics table corresponding to your package. the power column defines the vdds power supply for each ball. figure 4-3. sys_xtalin squarer input clock 4.1.4 sys_32k cmos input clock table 4-6 summarizes the electrical characteristics of the sys_32k input clock. table 4-6. sys_32k input clock electrical characteristics name description min typ max unit f frequency, sys_32k 32.768 khz c i input capacitance 1.6 pf r i input resistance 3 10 6 m ? table 4-7 details the input requirements of the sys_32k input clock. table 4-7. sys_32k input clock timing requirements (1) name description min typ max unit ck0 1 / t c(32k) frequency, sys_32k 32.768 khz t r(32k) rise time, sys_32k 10 ns t f(32k) fall time, sys_32k 10 ns t j(32k) frequency stability, sys_32k 200 ppm 136 clock specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-008 sys_xtalin osc0 osc1 osc1
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in this table, the transition times are calculated for 10%-90% of vdds. for more information on the corresponding vdds power supply name, please see the ball characteristics table corresponding to your package. the power column defines the vdds power supply for each ball. figure 4-4. sys_32k input clock 4.1.5 sys_altclk cmos input clock table 4-8 summarizes the electrical characteristics of the sys_altclk input clock. table 4-8. sys_altclk input clock electrical characteristics name description min typ max unit f frequency, sys_altclk 48 or 54 mhz ci input capacitance 1.6 pf ri input resistance 3 10 6 m ? table 4-9 details the input requirements of the sys_altclk input clock. table 4-9. sys_altclk input clock timing requirements (2) name description min typ max unit alt0 1 / t c(altclk) frequency, sys_altclk 48 or 54 mhz alt1 t w(altclk) pulse duration, sys_altclk low or high 0.49 * t c(altclk) 0.51 * t c(altclk) ns t j(altclk) peak-to-peak jitter (1) , sys_altclk -1% 1% t r(altclk) rise time, sys_altclk 10 ns t f(altclk) fall time, sys_altclk 10 ns t j(altclk) frequency stability, sys_altclk 50 ppm (1) peak-to-peak jitter is meant here as follows: C the maximum value is the difference between the longest measured clock period and the expected clock period C the minimum value is the difference between the shortest measured clock period and the expected clock period maximum and minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock period (2) in this table, the transition times are calculated for 10%-90% of vdds. for more information on the corresponding vdds power supply name, please see the ball characteristics table corresponding to your package. the power column defines the vdds power supply for each ball. figure 4-5. sys_altclk input clock copyright ? 2010 C 2011, texas instruments incorporated clock specifications 137 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-009 sys_32k ck0 ck1 ck1 swps038-010 sys_altclk alt0 alt1 alt1
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 4.2 output clocks specifications 4.2.1 sys_clkout1 output clock table 4-10 summarizes the sys_clkout1 ouput clock electrical characteristics. table 4-10. sys_clkout1 output clock electrical characteristics name description min typ max unit f frequency, sys_clkout1 sys_xtalin / sys_xtalout clock frequency mhz sc[0:1] = 00 (1) c l load capacitance (transmission line load + far end load) 4 60 pf z t transmission line impedance 30 70 ? l t transmission line length 2 20 cm sc[0:1] = 01 (1) c l load capacitance (transmission line load + far end load) 7 33 pf z t transmission line impedance 30 70 ? l t transmission line length 2 8 cm sc[0:1] = 10 (1) c l load capacitance (transmission line load + far end load) 2 21 pf z t transmission line impedance 30 70 ? l t transmission line length 1 6 cm (1) the mode is configured by bits sc0 and sc1 of the io cell. for more details, see the am/dm37x multimedia device technical reference manual ( sprugn4 ). table 4-11 details the sys_clkout1 ouput clock switching characteristics. table 4-11. sys_clkout1 output clock switching characteristics (6) name description min typ max unit co0 1 / t c(clkout1) frequency, sys_clkout1 sys_xtalin/sys_xtalout clock frequency mhz sc[0:1] = 00 (1) c l load capacitance 4 60 pf t j peak-to-peak jitter x (5) + 693 ps t jc2c cycle-to-cycle jitter x (5) + 705 ps t w(clkout1) pulse duration, sys_clkout1 low or high 0.45* tc(clkout 0.55* tc(clkout 1) 1) t r(clkout1) rise time, sys_clkout1 1 (2) (4) 15 (3) ns t f(clkout1) fall time, sys_clkout1 1 (2) (4) 15 (3) ns sc[0:1] = 01 (1) c l load capacitance 7 33 pf t j peak-to-peak jitter x (5) + 543 ps t jc2c cycle-to-cycle jitter x (5) + 555 ps t w(clkout1) pulse duration, sys_clkout1 low or high 0.45* tc(clkout 0.55* tc(clkout 1) 1) t r(clkout1) rise time, sys_clkout1 0.6 (2) (4) 7 (3) ns t f(clkout1) fall time, sys_clkout1 0.6 (2) (4) 7 (3) ns sc[0:1] = 10 (1) c l load capacitance 2 21 pf t j peak-to-peak jitter x (5) + 603 ps t jc2c cycle-to-cycle jitter x (5) + 615 ps t w(clkout1) pulse duration, sys_clkout1 low or high 0.47* tc(clkout 0.53* tc(clkout 1) 1) t r(clkout1) rise time, sys_clkout1 0.4 (2) (4) 5 (3) ns 138 clock specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 4-11. sys_clkout1 output clock switching characteristics (6) (continued) name description min typ max unit t f(clkout1) fall time, sys_clkout1 0.4 (2) (4) 5 (3) ns (1) the mode is configured by bits sc0 and sc1 of the io cell. for more details, see the am/dm37x multimedia device technical reference manual ( sprugn4 ). (2) at minimum load (3) at maximum load (maximum frequency 20 mhz) (4) caution: this creates emi parasitics up to 1.2 ns (5) x parameter corresponds to the input jitter contribution added at sys_xtalin input pin. for more information regarding the sys_xtalin input jitter requirement, see section 4.1.1 . (6) in this table, the transition times are calculated for 10%-90% of vdds. for more information on the corresponding vdds power supply name, please see the ball characteristics table corresponding to your package. the power column defines the vdds power supply for each ball. figure 4-6. sys_clkout1 output clock 4.2.2 sys_clkout2 output clock table 4-12 summarizes the sys_clkout2 ouput clock electrical characteristics. table 4-12. sys_clkout2 output clock electrical characteristics name description min typ max unit f frequency, sys_clkout2 sys_xtalin clock or core_dpll clock (1) or 54 mhz mhz, 96 mhz (2) c l load capacitance 2 22 pf z t transmission line impedance 30 70 ? l t transmission line length 1 6 cm (1) possible divider: 4, 8, or 16. (2) possible divider: 1, 2, 4, 8, or 16. table 4-13 details the sys_clkout2 ouput clock switching characteristics. table 4-13. sys_clkout2 output clock switching characteristics (8) name description min typ max unit co0 1 / t c(clkout2) frequency, sys_clkout2 sys_xtalin clock or core_dpll clock (3) or 54 mhz mhz, 96 mhz (4) t c(xtalin) cycle time, sys_xtalin 1 / sys_xtalin ns (mhz) t c(coredpll) cycle time, core_dpll (dpll3) (7) 1 / core_dpll ns (mhz) t c(54mhz) cycle time, 54mhz clock (dpll4) (7) 18.52 ns t c(96mhz) cycle time, 96mhz clock (dpll4) (7) 10.42 ns co1 t w(clkout2) pulse duration, sys_clkout2 low or high 0.49*tc(clkout 0.51*tc(clkout ns 2) 2) copyright ? 2010 C 2011, texas instruments incorporated clock specifications 139 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-011 sys_clkout1 co0 co1 co1
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 4-13. sys_clkout2 output clock switching characteristics (8) (continued) name description min typ max unit t j (5) peak-to-peak jitter source clock: x% (6) * ps sys_xtalin t c(xtalin) + 200 source clock: 4% * ps core_dpll t c(coredpll) + 200 source clock: 54mhz 4% * t c(54mhz) ps + 200 source clock: 96mhz 4% * t c(96mhz) ps + 200 t r(clkout2) rise time, sys_clkout2 1.5 (1) 5 (2) ns t f(clkout2) fall time, sys_clkout2 1.5 (1) 5 (2) ns (1) at minimum load (2) at maximum load (maximum frequency 104 mhz) (3) possible divider: 4, 8, 16 (4) possible divider: 1, 2, 4, 8, or 16 (5) peak-to-peak jitter is meant here as follows: C the maximum value is the difference between the longest measured clock period and the expected clock period C the minimum value is the difference between the shortest measured clock period and the expected clock period maximum and minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock period. (6) depending on the internal system clock divider configuration (prcm.prm_clksrc_ctrl[7:6], sysclkdiv bit field), the sys_xtalin input clock can be divided by 2 to provide the standard system clock (sys_clk) frequencies. for more information, see the power, reset, and clock management / prcm functional description / prcm clock manager functional description / external clock i/os / external clock inputs / high-frequency system clock section of am/dm37x multimedia device technical reference manual (literature number sprugn4 ). in x%, x represents then the internal system clock divider with following possible values: x = 1 or 2. (7) this cycle time specified here is the clock period of the clock going out of sys_clkout2. (8) in this table, the transition times are calculated for 10%-90% of vdds. for more information on the corresponding vdds power supply name, please see the ball characteristics table corresponding to your package. the power column defines the vdds power supply for each ball. figure 4-7. sys_clkout2 output clock 4.3 dpll and dll specifications note for more information, see power, reset, and clock management / prcm functional description / prcm clock manager functional description / internal clock generation / dplls section of the am/dm37x multimedia device technical reference manual ( sprugn4 ). the applicative subsystem integrates six dplls and a dll. the prm and cm drive those listed below. the main dplls are: ? dpll1 (mpu) ? dpll2 (iva) ? dpll3 (core) ? dpll4 (peripherals) ? dpll5 (second peripherals dpll) 140 clock specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-012 sys_clkout2 co0 co1 co1
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 4.3.1 dpll characteristics table 4-14 summarizes the dpll characteristics and assumes testing over recommended operating conditions. table 4-14. dpll1 - dpll2 - dpll3 - dpll5 characteristics name description min typ max unit comments vdda_dplls_dll supply voltage for dplls (mpu , iva, 1.71 1.8 1.91 v and core) and dll vdda_dpll_per supply voltage for dpll 1.71 1.8 1.91 v (peripherals) f input clkinp input frequency 0.032 52 mhz finp f internal internal reference frequency 0.032 52 mhz refclk f clkinphif clkinphif input frequency 10 1000 mhz finphif f clkinpulow clkinpulow input frequency 0.001 800 mhz f clkout clkout output frequency 10 (1) 1000 (2) mhz [m / (n + 1)] * finp * [1 / m2] f clkoutx2 clkoutx2 output frequency 20 (1) 2000 (2) mhz 2 * [m / (n + 1)] * finp * [1 / m2] f clkouthif clkouthif output frequency 10 (3) 1000 (4) mhz finphif / m3 20 (3) 2000 (4) 2 * [m / (n + 1)] * finp * [1 / m3] f dcoclkldo dcoclkldo output frequency 20 2000 mhz 2 * [m / (n + 1)] * finp t lock frequency lock time 1.9 + s 350*refclk p lock phase lock time 1.9 + s 500*refclk t relock-l relock time frequency lock (5) (low 1.9 + 70*refclk s dpll in low-power mode: power bypass) lowcurrstdby = 1 p relock-l relock time phase lock (5) (low 1.9 + s dpll in low-power mode: power bypass) 120*refclk lowcurrstdby = 1 t relock-f relock time frequency lock (5) (fast 0.05 + s dpll in normal mode: relock bypass) 70*refclk lowcurrstdby = 0 p relock-f relock time phase lock (5) (fast 0.05 + s dpll in normal mode: relock bypass) 120*refclk lowcurrstdby = 0 (1) the minimum frequencies on clkout and clkoutx2 are assuming m2 = 1. for m2 > 1, the minimum frequency on these clocks will further scale down by factor of m2. (2) the maximum frequencies on clkout and clkoutx2 are assuming m2 = 1. (3) the minimum frequency on clkouthif is assuming m3 = 1. for m3 > 1, the minimum frequency on this clock will further scale down by factor of m3. (4) the maximum frequency on clkouthif is assuming m3 = 1. (5) relock time assumes typical operating conditions, 10 c maximum temperature drift. table 4-15. dpll4 characteristics name description min typ max unit comments vdda_dpll_per supply voltage for dpll (peripherals) 1.71 1.8 1.91 v f input clkinp input clock frequency 0.5 60 mhz finp f internal refclk internal reference frequency 0.5 2.5 mhz refclk f clkinpulow clkinpulow bypass input 0.001 800 mhz frequency f clkout clkout output clock frequency 10 (1) 2000 (2) mhz [m / (n + 1)] * finp * [1 / m2] f dcoclkldo internal oscillator (dco) output clock 500 2000 mhz [m / (n + 1)] * finp frequency t lock frequency lock time 350*refclk s p lock phase lock time 500*refclk s t relock-l relock time frequency lock (3) (low 7.5 + s dpll in low-power mode: power bypass) 30*refclks lowcurrstdby = 1 copyright ? 2010 C 2011, texas instruments incorporated clock specifications 141 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 4-15. dpll4 characteristics (continued) name description min typ max unit comments p relock-l relock time phase lock (3) (low 7.5 + s dpll in low-power mode: power bypass) 125*refclks lowcurrstdby = 1 t relock-f relock time frequency lock (3) (fast na s relock bypass) p relock-f relock time phase lock (3) (fast na s relock bypass) (1) the minimum frequency on clkout is assuming m2 = 1. for m2 > 1, the minimum frequency on this clock will further scale down by factor of m2. (2) the maximum frequency on clkout is assuming m2 = 1. (3) relock time assumes typical operating conditions, 10 c maximum temperature drift. 4.3.2 dll characteristics table 4-16 summarizes the dll characteristics and assumes testing over recommended operating conditions. table 4-16. dll characteristics name description min typ max unit comments vdda_dplls_dll supply voltage for dplls (mpu , iva, and 1.71 1.8 1.91 v core) and dll f input input clock frequency (1) 66 120 200 mhz either application mode 0 and 1 t lock lock time 500 clocks t relock relock time (mode transitions through idle 500 ns idle to modemaxdelay mode) 250 450 clocks idle to application mode 1 or 0 1.88 3.38 s idle to application mode @133 mhz 1.50 2.71 s idle to application mode @166 mhz 1.25 2.25 s idle to application mode @200 mhz (1) maximum frequency for nominal conditions. 142 clock specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 4.3.3 dpll and dll noise isolation the noise filters (decoupling capacitors) are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. a noise filter is most effective when it is close to the device, because this minimizes the inductance of the circuit board wiring and interconnects. figure 4-8 illustrates an example of a noise filter. a. this circuit is provided only as an example. b. the filter must be located as close as possible to the device. figure 4-8. dpll noise filter table 4-17 specifies the noise filter requirements. table 4-17. dpll noise filter requirements (1) name min typ max unit filtering capacitor 50 100 150 nf (1) for more information, see io and analog voltage decoupling capacitors . 4.3.4 processor clocks table 4-18 through table 4-20 show the clocks ac performance values. table 4-18. processor voltages without smartreflex tm retentio opp50 opp100 opp130 (3) n min min typ max min typ max min typ max vdd1 (1) (2) 0.8 0.92 0.97 1.02 1.08 1.14 1.2 1.21 1.27 1.33 (v) (1) at ball level. (2) minimum opp voltage values defined in this table include any voltage transient. (3) opp130 is not available above t j of 90c. table 4-19. processor voltages with smartreflex tm retentio opp50 opp100 opp130 (4) opp1g (4) (5) (6) n min min typ max min typ max min typ max min typ max copyright ? 2010 C 2011, texas instruments incorporated clock specifications 143 submit documentation feedback product folder link(s): dm3730 dm3725 dpll_mpu dpll_core dll dpll5 dpll4 vdda_dplls_dll vdda_dpll_per c noise filter c noise filter 030-017 dpll_iva
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 4-19. processor voltages with smartreflex tm (continued) retentio opp50 opp100 opp130 (4) opp1g (4) (5) (6) n vdd1 (1) (2) 0.8 0.92 0.97 1.02 1.08 1.14 1.2 1.21 1.27 1.33 1.28 1.33 1.38 (3) (v) (1) at ball level. (2) these vdd1 (vdd_mpu_iva) values are the required voltage ranges prior to enabling the smartreflex avs feature. after calibration, the minimum voltage may be lower than this specification. (3) minimum opp voltage values defined in this table include any voltage transient. (4) opp130 and opp1g are not available above t j of 90c. (5) opp1g is a high performance operating point which has following requirements: C abb ldo must be set to fbb (forward body bias) mode when switching to this opp. it requires having a 1 f capacitor connected to cap_vdd_bb_mpu_iva. C avs (adaptive voltage scaling) power technique must be used to achieve optimum operating voltage. (6) based on dm3730 pcb constraints, the vdd_mpu_iva (vdd1) voltage value calibrated before enabling smartreflex ? is recommended to be 1.38v. minimum (1.28v) and typical (1.33v) values provided can be achieved only with very good power delivery network design. for more information on vdd_mpu_iva power delivery network design requirements, see the pcb design requirements for vdd_mpu_iva power distribution network for ti omap3630, am37xx, and dm37xx microprocessors (sprabj7) application note. table 4-20. processor clocks opp50 opp100 opp130 opp1g (2) description source clock max ratio max ratio max ratio max ratio freq.(mhz) freq.(mhz) freq.(mhz) freq.(mhz) dpll1 - 1200 - 1200 - 1600 - 2000 - locked frequency dpll1clko dpll1 300 2 *(m2 = 600 2 *(m2 = 800 2 *(m2 = 1000 2 *(m2 = ut_m2 locked 2) (1) (4) 1) (1) (4) 1) (1) (4) 1) (1) (4) frequency dpll2 - 1040 - 1040 - 1320 - 1600 - locked frequency dpll2clko dpll2 260 2 *(m2 = 520 2 *(m2 = 660 2 *(m2 = 800 2 *(m2 = ut_m2 locked 2) (1) (4) 2) (1) (4) 2) (1) (4) 2) (1) (4) frequency arm_fclk dpll1clko 300 1 600 1 800 1 1000 1 ut_m2 iva_clk dpll2clko 260 1 520 1 660 1 800 1 ut_m2 (1) this ratio is configurable by software programming. for more information, see the am/dm37x multimedia device technical reference manual ( sprugn4 ). (2) opp1g is a high performance operating point which has following requirements: C abb ldo must be set to fbb (forward body bias) mode when switching to this opp. it requires having a 1 f capacitor connected to cap_vdd_bb_mpu_iva. C avs (adaptive voltage scaling) power technique must be used to achieve optimum operating voltage. (3) for more information about arm_fclk and iva2_clk processor clocks configuration, see the power, reset, and clock management / prcm functional description / prcm clock manager functional description / clock configurations / processor clock configurations section or the mpu subsystem / mpu subsystem integration / mpu subsystem clock and reset distribution / clock distribution section of the am/dm37x multimedia device technical reference manual ( sprugn4 ). (4) the dpll ratios documented in this table are recommended ratios. other values may apply. 144 clock specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 4.3.5 device core clocks table 4-21 and table 4-22 show the device core clocks ac performance values. table 4-21. device core voltages retention opp50 opp100 min min typ max min typ max vdd2 (1) (2) (3) (v) 0.8 0.90 0.95 1.00 1.08 1.14 1.20 (1) at ball level. (2) minimum opp voltage values defined in this table include any voltage transient. (3) when smartreflex ? is not used, these values define the required voltage range. when smartreflex ? will be used, these voltages are the required voltage range prior to enabling the smartreflex ? feature. after calibration, the minimum voltage may be lower than this specification. table 4-22. device core clocks opp50 opp100 descripti source max ratio max ratio max ratio max ratio max ratio max ratio on freq.(mh freq.(mh freq.(mh freq.(mh freq.(mh freq.(mh z) z) z) z) z) z) dpll3 - 800 - 664 - 400 - 800 - 664 - 532 - locked frequenc y dpll3c dpll3 200 2 *(m2 = 166 2 *(m2 = 200 2 *(m2 = 400 2 *(m2 = 332 2 *(m2 = 266 2 *(m2 = lkout_ locked 2) (1) (2) 1) (1) (2) 1) (1) (2) 1) (1) (2) 1) (1) (2) 1) (1) (2) m2 frequenc y core_c dpll3c 200 1 166 1 200 1 400 1 332 1 266 1 lk lkout_ m2 l3_iclk core_c 100 2 (1) 83 2 (1) 100 2 (1) 200 2 (1) 166 2 (1) 133 2 (1) lk l4_iclk l3_iclk 50 2 (1) 41.5 2 (1) 50 2 (1) 100 2 (1) 83 2 (1) 66.5 2 (1) sdrc_c l3_iclk 100 1 83 1 100 1 200 1 166 1 133 1 lk gpmc_c l3_iclk 50 2 (1) 41.5 2 (1) 50 2 (1) 100 2 (1) 83 2 (1) 66.5 2 (1) lk (1) this ratio is configurable by software programming. for more information, see the am/dm37x multimedia device technical reference manual ( sprugn4 ). (2) the dpll ratios documented in this table are recommended ratios. other values may apply. 4.3.6 graphic accelerator (sgx) clocks table 4-23 and table 4-24 show the recommended v dd2 (corresponding to vdd_core, core and sgx voltage at ball level) voltages ranges and the standard graphic accelerator (sgx) clocks speed characteristics vs v dd2 . table 4-23. graphic accelerator voltages opp 100 (2) min typical max v dd2 (1) (3) (4) (v) 1.08 1.14 1.20 (1) at ball level. (2) sgx (graphic accelerator) is not available in the opp50 operating point. (3) when smartreflex ? is not used, these values define the required voltage range. when smartreflex ? will be used, these voltages are the required voltage range prior to enabling the smartreflex ? feature. after calibration, the minimum voltage may be lower than this specification. (4) minimum opp voltage values defined in this table include any voltage transient. copyright ? 2010 C 2011, texas instruments incorporated clock specifications 145 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 4-24. graphic accelerator clocks (2) opp 100 (2) max freq max freq max freq description source clock ratio ratio ratio (mhz) (mhz) (mhz) dpll3 locked frequency 800 664 532 dpll4 locked frequency 1728 1728 1728 1 * (m2 = 1 * (m2 = 1 * (m2 = dpll3clkoutx2_m2 dpll3 locked frequency 800 664 532 1) (1) (3) 1) (1) (3) 1) (1) (3) 2 * (m2 = 2 * (m2 = 2 * (m2 = dpll3clkout_m2 dpll3 locked frequency 400 332 266 1) (1) (3) 1) (1) (3) 1) (1) (3) 1 * (m2 = 1 * (m2 = 1 * (m2 = dpll4clkout_m2 dpll4 locked frequency 192 192 192 9) (1) (3) 9) (1) (3) 9) (1) (3) core_clk dpll4 locked frequency 400 1 332 1 266 1 corex2_clk dpll3clkoutx2_m2 800 1 664 1 532 1 sgx_192m_fclk dpll4clkout_m2 192 1 192 1 192 1 sgx C option 1 core_clk 200 2 166 2 133 2 sgx C option 2 corex2_clk 177.3 3 sgx C option 3 sgx_192m_fclk 192 1 192 1 192 1 (1) this ratio is configurable by software programming. for more information, see the am/dm37x multimedia device technical reference manual ( sprugn4 ). (2) sgx (graphic accelerator) is not available in opp50 operating point. (3) the dpll ratios documented in this table are recommended ratios. other values may apply. 146 clock specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 5 video dac specifications note for more information regarding the videodac architecture, see the display subsystem / display subsystem functional description / video encoder functionalities / video dac stage architecture and control section of am/dm37x technical reference manual (literature number sprugn4 ). 5.1 tvout buffer mode (dac + buffer) note avdac normal mode (dac + buffer), higher values of the dac input code provided by the video encoder will result in lower output voltage due to the inverting configuration of the tvout buffer. see figure 5-4 for more details on the relation between the composite video signal levels and the dac code values for normal mode of operation. in avdac bypass mode (dac only), higher values of the dac input code will result in higher output voltage, as the tvout buffer path is bypassed. the connection for this tvout buffer mode (dac + buffer) normal mode of operation is shown in figure 5-1 . the default mode of operation is dc coupling. for more information regarding the recommended values of the external components, see section 5.4 , electrical specifications over recommended operating conditions . figure 5-1. recommended loading conditions for tvout buffer mode (1) (1) in single-channel configuration only channel-1 is used. copyright ? 2010 C 2011, texas instruments incorporated video dac specifications 147 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-125 = external pin vref tvdet tvbuf + C i dac avdac vssa_dacvdda_dac cvideo1_out cvideo1_vfb cvideo1_rset r set r load r out
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 5.2 tvout bypass mode (dac only) in this case, tvout bypass input is high and the tvout buffer is bypassed (for more information, see section 5.5 , tvout bypass mode specifications (dac-only) electrical specifications over recommended operating conditions ). figure 5-2 shows the connection. for more information regarding the recommended values of the external components, see section 5.4 , electrical specifications over recommended operating conditions . figure 5-2. recommended loading conditions for tvout bypass mode (1) (1) in single-channel configuration only channel-1 is used. 148 video dac specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-131 = external pin vref tvdet tvbuf + C i dac avdac vssa_dacvdda_dac cvideo1_out cvideo1_vfb cvideo1_rset r set r load offoff
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 5.3 tvout bypass mode in dual-channel configuration in this case, tvout bypass input is high and the tvout buffer is bypassed (for more information, see section 5.5 , tvout bypass mode specifications (dac-only) electrical specifications over recommended operating conditions ). figure 5-3 shows the connection. for more information regarding the recommended values of the external components, see section 5.4 , electrical specifications over recommended operating conditions . figure 5-3. recommended loading conditions for tvout bypass mode in dual-channel configuration (1) (1) here are some connections recommendations: C an external resistor r set = 10 k ( 1%) is recommended to be connected to the cvideo1_rset signal of channel 1. C the cvideo1_rset signal of channel 2 is left unconnected. C external resistors r load1load2 = 1.5 k ( 1%) is recommended to be connected to cvideo1_vfb or cvideo2_vfb each channel. copyright ? 2010 C 2011, texas instruments incorporated video dac specifications 149 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 5.4 electrical specifications over recommended operating conditions note high-swing mode is the default mode. the low-swing mode is not compliant with the ntsc and pal video-standards. it shall be used only for backwards compatibility to am/dm37x. ? tvout dc high swing mode: C r out1/2 = 2.7 k ( 1%) C r set = 4.7 k ( 1%) C r load = 75 ( 5%) C z cable = 75 ( 5%) ? tvout dc low swing mode: C r out1/2 = 2.7 k ( 1%) C r set = 6.8 k ( 1%) C r load = 75 ( 5%) C z cable = 75 ( 5%) ? tvout ac high swing mode: C r out1/2 = 2.7 k ( 1%) C r set = 4.7 k ( 1%) C r load = 75 ( 5%) C z cable = 75 ( 5%) C c ac = 220 f ( 5%) ? tvout ac low swing mode: C r out1/2 = 2.7 k ( 1%) C r set = 6.8 k ( 1%) C r load = 75 ( 5%) C z cable = 75 ( 5%) C c ac = 220 f ( 5%) table 5-1. dac C static electrical specifications (8) parameter conditions/assumptions min typ max unit r resolution 10 bits dc accuracy inl (1) integral non-linearity (inl) 50 to 111 input code range C 6 6 lsb integral non-linearity (inl) 111 to 895 input code range C 4 4 signal video range integral non-linearity (inl) 783 to 1007 input code range C 5 5 synchronization pulse dnl (2) differential nonlinearity 111 to 895 input code range C 2.5 2.5 lsb analog output - output voltage 0 to 1023 input low-swing mode 0.70 0.88 1.00 v code range, high-swing mode 1.2 1.3 1.5 r load = 75 - gain error - low-swing mode C 20 20 % fs high-swing mode C 10 10 r vout output impedance 67.5 75.0 82.5 reference v ref internal band gap voltage reference 0.55 v 150 video dac specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 5-1. dac C static electrical specifications (8) (continued) parameter conditions/assumptions min typ max unit power consumption i vdda-up analog supply dc mode no average current on vdda_dac, no 4.5 6.5 8.5 ma current (4) load load, 2 channels input code 50 (maximum output ac mode no 19 28 37 voltage) load full load 75- 19 28 37 load i vdda-up (peak) peak analog supply current lasts less than 1 ns 60 ma i vdd-up digital supply current (5) average current, measured at f clk 2 ma = 54 mhz, f out = 2 mhz sine wave, vdd = 1.1 v i vdd-up (peak) peak digital supply current (6) peak current, full-scale transition 8 ma lasting less than 1 ns i vdda-down (9) analog supply current, total power t = 30 o c, vdda_dac = 1.8 v, no 12 a down (9) load i vdda-stdby (9) analog supply current, standby mode (9) bandgap and internal ldo are on, 90 180 270 a all other analog blocks are off, no load, t = 30 c o i vdd-down(pm) (9) digital supply current, total power t = 30 o c, full low-swing mode 2 a down (9) or partial power high-swing mode 6 management i vdd-down(nopm) digital supply current, total power down t = 30 o c, vdd = 1.1 v, no power 60 a (no power management) management (1) the inl is measured at the output of the dac (accessible at an external pin during bypass mode). the inl at code 783 equals 0. (2) the dnl is measured at the output of the dac (accessible at an external pin during bypass mode). the inl at code 783 equals 0. (3) reference psr measures the effect of a supply disturbance at cvideo1_out and cvideo2_out. (4) the analog supply current i vdda is directly proportional to the full-scale output current ifs and is insensitive to f clk . (5) the digital supply current i vdd is dependent on the digital input waveform, the dac update rate f clk , and the digital supply vdd. (6) the peak digital supply current occurs at full-scale transition for duration less than 1 ns. (7) see section 5.6 , analog supply (vdda_dac) noise requirements , for actual maximum ripple allowed on vdda_dac. (8) for more information on code range definition, see figure 5-4 . (9) for more information on avdac power-up, power-down, and standby mode configurations, see display subsystem / display subsystem functional description / video encoder functionalities / video dac stage power management section of am/dm37x technical reference manual (literature number sprugn4 ). note high-swing mode is the default mode. the low-swing mode is not compliant with the ntsc and pal video-standards. it is used only for backwards compatibility to am/dm37x. copyright ? 2010 C 2011, texas instruments incorporated video dac specifications 151 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 5-2. video dac C dynamic electrical specifications (6) paramet conditions/assumptions min typ max unit er f clk (1) output update rate equal to input clock frequency 54 60 mhz clock jitter rms clock jitter required in order to 40 70 ps assure 10-bit accuracy attenuation at 5.1 mhz corner frequency for dc mode 1.5 db signal ac mode bw signal bandwidth 3 db dc mode 6 mhz ac mode differential gain (2) 111 to 895 input code dc mode C 5% 5% range ac mode C 5% 5% differential phase (2) 111 to 895 input code dc mode C 3 o 3 o range ac mode C 3 o 3 o sfdr within bandwidth 1 khz to f clk = 54 mhz, f out = 1 dc mode 40 50 70 db 6 mhz mhz, sine wane input, ac mode 111 to 895 input code range snr within bandwidth 1 khz to f clk = 54 mhz, f out = 1 dc mode 50 54 75 db 6 mhz mhz, sine wane input, ac mode 256 to 768 input code range psr (4) power supply rejection (up 100 mvpp at 6 mhz, input code 895 6 (4) db to 6 mhz) crosstalk between the two video C 50 C 40 db channels c load tvout (cvideo_out1 and total decoupling capacity from 300 pf cvideo_out2) stability, cvideo_out1 or cvideo_out2 to ground, tvout decoupling c load1 capacity c tot tvout stability, total total decoupling capacity: c tot = c load1 600 pf tvout decoupling + c load2 capacity (1) for internal input clock information, see the dss chapter of am/dm37x technical reference manual (literature number sprugn4 ). (2) the differential gain and phase value is for dc coupling. note that there is degradation for the ac coupling. the differential gain and phase are measured with respect to the gain and phase of the burst signal ( C 20 to 20 ire) (3) the snr value is for dc coupling. (4) psr measures the effect of a supply disturbance at cvideo1_out and cvideo2_out. (5) the flat band measurement is done at 500 khz for characterizing the attenuation at 5.1 mhz. (6) for more information on code range definition, see figure 5-4 . 152 video dac specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 5-4 describes the composite video signal levels. figure 5-4. composite video signal levels (1) (2) (1) the 1.3 v pp (peak-to-peak) is referring to the output signal at cvideo1_out in the dac + buffer composite-video mode. note that the 1.3 v pp must apply to both cvideo1_out and cvideo2_out in dac + buffer s-video mode (dual-dac mode configured for ac or dc coupling). (2) in avdac normal mode (dac + buffer), higher values of the dac input code provided by the video encoder will result in lower output voltage due to the inverting configuration of the tvout buffer. see figure 5-4 for more details on the relation between the composite video signal levels and the dac code values for normal mode of operation. in avdac bypass mode (dac only), higher values of the dac input code will result in higher output voltage, as the tvoutbuffer path is bypassed. 5.5 tvout bypass mode specifications (dac-only) electrical specifications over recommended operating conditions note the electrical characteristics for single- and dual-channel bypass modes are the same except that the active current will double in the dual-channel configuration. copyright ? 2010 C 2011, texas instruments incorporated video dac specifications 153 submit documentation feedback product folder link(s): dm3730 dm3725 standard video range tvout 10-bit dac code ire units normal mode 0 50 111 223 741 783 895 1007 1023 140 131 120100 20 7.5 0 -20-40 1.3 v * pp sync level black level blanking level peak level white level swps038-130
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com ? bypass mode C r load = 1.5 k ( 1%) C r set = 10 k ( 1%) table 5-3. dac static electrical specifications bypass mode (2) parameter conditions/assumptions min typ max unit r resolution 10 bits dc accuracy inl (1) integral nonlinearity (inl) 37 to 954 input code range, r load = 1.5 k C 1 1 lsb dnl (1) differential nonlinearity 37 to 954 input code range, r load = 1.5 k C 1 1 lsb analog output - output voltage r load = 1.5 k 0.6 0.7 0.77 v - output current r load = 1.5 k 0.6 0.7 0.77 v - gain error - C 10 10 % fs power consumption i vdda-up analog supply current average current on vdda_dac, r load = 1.5 k 0.7 1.0 1.4 ma input code 1023 i vdda-down analog supply current, total t = 30c o , vdda_dac = 1.8 v, no load 12 a power down i vdda-stdby analog supply current, bandgap and internal ldo are on, all other 90 180 270 a standby mode analog blocks are off, no load, t = 30c o (1) in bypass mode, output node is cvideo1_out and cvideo2_out nodes. for more information, see section 5.2 , tvout bypass mode (dac only) or section 5.3 , tvout bypass mode in dual-channel configuration . (2) for more information on code range definition, see figure 5-4 . table 5-4. video dac dynamic electrical specifications bypass mode parameter conditions/assumptions min typ max unit f clk output update rate equal to input clock frequency 54 60 mhz clock jitter rms clock jitter required in order to 40 70 ps assure 10-bit accuracy bw signal bandwidth 3db 6 mhz sfdr within bandwidth 1 khz to 6 mhz f clk = 54 mhz, f out = 1 mhz, sine 40 50 70 db wave input, 111 to 895 input code range snr within bandwidth 1 khz to 6 mhz f clk = 54 mhz, f out = 1 mhz, sine 50 54 75 db wave input, 256 to 768 input code range psr power supply rejection (up to 6 mhz) 100 mvpp at 6 mhz, input code 895 6 (1) db (1) for more information on code range definition, see figure 5-4 . 5.6 analog supply (vdda_dac) noise requirements in order to assure 10-bit accuracy of the dac analog output, the analog supply vdda_dac has to meet the noise requirements stated in this section. the dac power supply rejection ratio (psrr) is defined as the relative variation of the full-scale output current divided by the supply variation. thus, it is expressed in percentage of full-scale range (fsr) per volt of supply variation as shown in the following equation: 154 video dac specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 depending on frequency, the psrr is defined in table 5-5 . table 5-5. video dac C power supply rejection ratio supply noise psrr % fsr/v frequency 0 to 100 khz 1 > 100 khz the rejection decreases 20 db/dec. example: at 1 mhz the psrr is 10% of fsr/v. a graphic representation is shown in figure 5-5 . figure 5-5. video dac C power supply rejection ratio to ensure that the dac sfdr specification is met, the psrr values and the clock jitter requirements translate to the following limits on vdda_dac (for the video dac). the maximum peak-to-peak noise on vdda (ripple) is defined in table 5-6 . table 5-6. video dac C maximum peak-to-peak noise on vdda_dac tone frequency maximum peak-to-peak noise on vdda_dac 0 to 100 khz < 30 mv pp > 100 khz decreases 20 db/dec. example: at 1 mhz the maximum is 3 mv pp the maximum noise spectral density (white noise) is defined in table 5-7 . table 5-7. video dac C maximum noise spectral density supply noise bandwidth maximum supply noise density 0 to 100 khz < 20 v / hz > 100 khz decreases 20 db/dec. example: at 1 mhz the maximum noise density is 2 v / hz copyright ? 2010 C 2011, texas instruments incorporated video dac specifications 155 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com because the dac psrr deteriorates at a rate of 20 db/dec after 100 khz, it is highly recommended to have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: section 5.7 , external component value choice ). 156 video dac specifications copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 5.7 external component value choice the output current i dacout appearing at the output of the 10-bit dac is a function of both the input code dac_code (ranging from 0 to 1023) and i dacmax and can be expressed as: i dacout = i ref * (dac_code / 120) (1) the maximum output current i dacmax from the dac is given by: i dacmax = i ref * 1023 / 120 (2) the reference current, i ref , is set by a combination of internal and external resistors in series, r ref , and an internal reference voltage, v ref , and is given by: i ref = v ref / r ref (3) typically, v ref = 0.55 v and r ref = 9.4 k in tvout high-swing mode. the video signal voltage at cvideo_out1 and cvideo_out2 nodes can be written as (excluding the offset voltage): v tvout = 35 * r load * i dacmax * (1 C dac_code / 1023) (4) figure 5-6 shows the cvideo_out1 and cvideo_out2 transfer function. regarding the typical composite video signal levels versus the dac input code, for more information on code range definition, see figure 5-4 . regarding the typical values of the typical values for r out1/2 and r set resistors, as well for c out capacitor, for different modes of the tv display interface, see the display subsystem / display subsystem environment / tv display support section of am/dm37x technical reference manual (literature number sprugn4 ). figure 5-6. cvideo_out1 and cvideo_ou2 transfer function note the dc levels (voffset) will be shifted due to process variations. copyright ? 2010 C 2011, texas instruments incorporated video dac specifications 157 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6 timing requirements and switching characteristics 6.1 timing test conditions all timing requirements and switching characteristics are valid over the recommended operating conditions unless otherwise specified. 6.2 interface clock specifications 6.2.1 interface clock terminology the interface clock is used at the system level to sequence the data and/or to control transfers accordingly with the interface protocol. 6.2.2 interface clock frequency the two interface clock characteristics are: ? the maximum clock frequency ? the maximum operating frequency the interface clock frequency documented in this document is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. this frequency defines the maximum limit supported by the device ic and doesn t take into account any system consideration (pcb, peripherals). the system designer will have to consider these system considerations and the device ic timing characteristics as well, to define properly the maximum operating frequency, which corresponds to the maximum frequency supported to transfer the data on this interface. 6.2.3 clock jitter specifications jitter is a phase noise, which may alter different characteristics of a clock signal. the jitter specified in this document is the time difference between the typical cycle period and the actual cycle period affected by noise sources on the clock. the cycle (or period) jitter terminology will be used to identify this type of jitter. figure 6-1. cycle (or period) jitter note max. cycle jitter = max (ti) min. cycle jitter = min (ti) jitter standard deviation (or rms jitter) = standard deviation (ti) 6.2.4 clock duty cycle error the maximum duty cycle error is the difference between the absolute value of the maximum high-level pulse duration or the maximum low-level pulse duration and the typical pulse duration value. ? maximum pulse duration = typical pulse duration + maximum duty cycle error ? minimum pulse duration = typical pulse duration - maximum duty cycle error 158 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-013 tnC1 tn tn+1
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 6.3 timing parameters the timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with jedec standard 100. to shorten the symbols, some of pin names and other related terminologies have been abbreviated as follows: table 6-1. timing parameters subscripts symbol parameter c cycle time (period) d delay time dis disable time en enable time h hold time su setup time start start bit t transition time v valid time w pulse duration (width) x unknown, changing, or don t care level f fall time h high l low r rise time v valid iv invalid ae active edge fe first edge le last edge z high impedance copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 159 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.4 external memory interfaces the device includes the following external memory interfaces: ? general-purpose memory controller (gpmc) ? sdram controller (sdrc) 6.4.1 general-purpose memory controller (gpmc) note for more information, see memory subsystem / general-purpose memory controller section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the gpmc is the unified memory controller used to interface external memory devices such as: ? asynchronous sram-like memories and asic devices ? asynchronous page mode and synchronous burst nor flash ? nand flash 6.4.1.1 gpmc/nor flash synchronous mode table 6-3 and table 6-4 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-2 through figure 6-6 ). table 6-2. gpmc/nor flash timing conditions synchronous mode timing condition parameter value unit input conditions t r input signal rise time 1.8 ns t f input signal fall time 1.8 ns output conditions c load output load capacitance (1) 12 pf (1) the load setting of the io buffer: lb0 = 1. table 6-3. gpmc/nor flash timing requirements synchronous mode (1) no. parameter opp100 opp50 unit min max min max f12 t su(dv-clkh) setup time, input data gpmc_d[15:0] valid before 2.3 2.3 ns output clock gpmc_clk high f13 t h(clkh-dv) hold time, input data gpmc_d[15:0] valid after output 1.5 1.5 ns clock gpmc_clk high f21 t su(waitv-clkh) setup time, input wait gpmc_waitx (2) valid before 2.3 2.3 ns output clock gpmc_clk high f22 t h(clkh-waitv) hold time, input wait gpmc_waitx (2) valid after output 1.9 1.9 ns clock gpmc_clk high (1) see section 4.3.4 , processor clocks . (2) in gpmc_waitx, x is equal to 0, 1, 2, or 3. table 6-4. gpmc/nor flash switching characteristics synchronous mode (2) (18) no. parameter opp100 opp50 unit min max min max f0 1 / t c(clk) frequency (15) , output clock gpmc_clk 100 100 mhz f1 t w(clkh) typical pulse duration, output clock gpmc_clk high 0.5p (12) 0.5p (12) ns f1 t w(clkl) typical pulse duration, output clock gpmc_clk low 0.5p (12) 0.5p (12) ns 160 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-4. gpmc/nor flash switching characteristics synchronous mode (2) (18) (continued) no. parameter opp100 opp50 unit min max min max t dc(clk) duty cycle error, output clock gpmc_clk C 500 500 C 500 500 ps t j(clk) jitter standard deviation (16) , output clock gpmc_clk 33.33 33.33 ps t r(clk) rise time, output clock gpmc_clk 1.6 1.6 ns t f(clk) fall time, output clock gpmc_clk 1.6 1.6 ns t r(do) rise time, output data gpmc_d[15:0] 2 2 ns t f(do) fall time, output data gpmc_d[15:0] 2 2 ns f2 t d(clkh-ncsv) delay time, output clock gpmc_clk rising edge to f (6) C 1.9 f (6) + 3.3 f (6) C 1.9 f (6) + 3.3 ns output chip select gpmc_ncsx (11) transition f3 t d(clkh-ncsiv) delay time, output clock gpmc_clk rising edge to e (5) C 1.9 e (5) + 3.3 e (5) C 1.9 e (5) + 3.3 ns output chip select gpmc_ncsx (11) invalid f4 t d(av-clk) delay time, output address gpmc_a[27:1] valid to b (2) C 4.1 b (2) + 2.1 b (2) C 4.1 b (2) + 2.1 ns output clock gpmc_clk first edge f5 t d(clkh-aiv) delay time, output clock gpmc_clk rising edge to C 2.1 C 2.1 ns output address gpmc_a[27:1] invalid f6 t d(nbev-clk) delay time, output lower byte enable/command latch b (2) C 1.2 b (2) + 2.2 b (2) C 1.2 b (2) + 2.2 ns enable gpmc_nbe0_cle, output upper byte enable gpmc_nbe1 valid to output clock gpmc_clk first edge f7 t d(clkh-nbeiv) delay time, output clock gpmc_clk rising edge to d (4) C 2.2 d (4) + 1.2 d (4) C 2.2 d (4) + 1.2 ns output lower byte enable/command latch enable gpmc_nbe0_cle, output upper byte enable gpmc_nbe1 invalid f8 t d(clkh-nadv) delay time, output clock gpmc_clk rising edge to g (7) + 0.8 g (7) + 2.2 g (7) + 0.8 g (7) + 2.2 ns output address valid/address latch enable gpmc_nadv_ale transition f9 t d(clkh-nadviv) delay time, output clock gpmc_clk rising edge to d (4) C 1.9 d (4) + 4.1 d (4) C 1.9 d (4) + 4.1 ns output address valid/address latch enable gpmc_nadv_ale invalid f10 t d(clkh-noe) delay time, output clock gpmc_clk rising edge to h (8) C 2.1 h (8) + 2.1 h (8) C 2.1 h (8) + 2.1 ns output enable gpmc_noe transition f11 t d(clkh-noeiv) delay time, output clock gpmc_clk rising edge to e (5) C 2.1 e (5) + 2.1 e (5) C 2.1 e (5) + 2.1 ns output enable gpmc_noe invalid f14 t d(clkh-nwe) delay time, output clock gpmc_clk rising edge to i (9) C 1.9 i (9) + 4.1 i (9) C 1.9 i (9) + 4.1 ns output write enable gpmc_nwe transition f15 t d(clkh-do) delay time, output clock gpmc_clk rising edge to j (10) C j (10) + j (10) C j (10) + ns output data gpmc_d[15:0] transition 1.7 1.2 1.7 1.2 f17 t d(clkh-nbe) delay time, output clock gpmc_clk rising edge to j (10) C j (10) + j (10) C j (10) + ns output lower byte enable/command latch enable 2.2 1.2 2.2 1.2 gpmc_nbe0_cle transition f18 t w(ncsv) pulse duration, output chip select read a (1) a (1) ns gpmc_ncsx (11) low write a (1) a (1) ns f19 t w(nbev) pulse duration, output lower byte read c (3) c (3) ns enable/command latch enable write c (3) c (3) ns gpmc_nbe0_cle, output upper byte enable gpmc_nbe1 low f20 t w(nadvv) pulse duration, output address read k (13) k (13) ns valid/address latch enable gpmc_nadv_ale write k (13) k (13) ns low f23 t d(clkh-iodir) delay time, output clock gpmc_clk rising edge to h (8) C 2.1 h (8) + 4.1 h (8) C 2.1 h (8) + 4.1 ns output io direction control gpmc_io_dir high (in direction) f24 t d(clkh-iodiriv) delay time, output clock gpmc_clk rising edge to m (17) C m (17) + m (17) C m (17) + ns output io direction control gpmc_io_dir low (out 2.1 4.1 2.1 4.1 direction) copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 161 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) for single read: a = (csrdofftime C csontime) * (timeparagranularity + 1) * gpmc_fclk (14) for burst read: a = (csrdofftime C csontime + (n C 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (14) for burst write: a = (cswrofftime C csontime + (n C 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (14) with n being the page burst access number. (2) b = clkactivationtime * gpmc_fclk (14) (3) for single read: c = rdcycletime * (timeparagranularity + 1) * gpmc_fclk (14) for burst read: c = (rdcycletime + (n C 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (14) for burst write: c = (wrcycletime + (n C 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (14) with n being the page burst access number. (4) for single read: d = (rdcycletime C accesstime) * (timeparagranularity + 1) * gpmc_fclk (14) for burst read: d = (rdcycletime C accesstime) * (timeparagranularity + 1) * gpmc_fclk (14) for burst write: d = (wrcycletime C accesstime) * (timeparagranularity + 1) * gpmc_fclk (14) (5) for single read: e = (csrdofftime C accesstime) * (timeparagranularity + 1) * gpmc_fclk (14) for burst read: e = (csrdofftime C accesstime) * (timeparagranularity + 1) * gpmc_fclk (14) for burst write: e = (cswrofftime C accesstime) * (timeparagranularity + 1) * gpmc_fclk (14) (6) for ncs falling edge (cs activated): C case gpmcfclkdivider = 0: C f = 0.5 * csextradelay * gpmc_fclk (14) C case gpmcfclkdivider = 1: C f = 0.5 * csextradelay * gpmc_fclk (14) if (clkactivationtime and csontime are odd) or (clkactivationtime and csontime are even) C f = (1 + 0.5 * csextradelay) * gpmc_fclk (14) otherwise C case gpmcfclkdivider = 2: C f = 0.5 * csextradelay * gpmc_fclk (14) if ((csontime C clkactivationtime) is a multiple of 3) C f = (1 + 0.5 * csextradelay) * gpmc_fclk (14) if ((csontime C clkactivationtime C 1) is a multiple of 3) C f = (2 + 0.5 * csextradelay) * gpmc_fclk (14) if ((csontime C clkactivationtime C 2) is a multiple of 3) (7) for adv falling edge (adv activated): C case gpmcfclkdivider = 0: C g = 0.5 * advextradelay * gpmc_fclk (14) C case gpmcfclkdivider = 1: C g = 0.5 * advextradelay * gpmc_fclk (14) if (clkactivationtime and advontime are odd) or (clkactivationtime and advontime are even) C g = (1 + 0.5 * advextradelay) * gpmc_fclk (14) otherwise C case gpmcfclkdivider = 2: C g = 0.5 * advextradelay * gpmc_fclk (14) if ((advontime C clkactivationtime) is a multiple of 3) C g = (1 + 0.5 * advextradelay) * gpmc_fclk (14) if ((advontime C clkactivationtime C 1) is a multiple of 3) C g = (2 + 0.5 * advextradelay) * gpmc_fclk (14) if ((advontime C clkactivationtime C 2) is a multiple of 3) for adv rising edge (adv deactivated) in reading mode: C case gpmcfclkdivider = 0: C g = 0.5 * advextradelay * gpmc_fclk (14) C case gpmcfclkdivider = 1: C g = 0.5 * advextradelay * gpmc_fclk (14) if (clkactivationtime and advrdofftime are odd) or (clkactivationtime and advrdofftime are even) C g = (1 + 0.5 * advextradelay) * gpmc_fclk (14) otherwise C case gpmcfclkdivider = 2: C g = 0.5 * advextradelay * gpmc_fclk (14) if ((advrdofftime C clkactivationtime) is a multiple of 3) C g = (1 + 0.5 * advextradelay) * gpmc_fclk (14) if ((advrdofftime C clkactivationtime C 1) is a multiple of 3) C g = (2 + 0.5 * advextradelay) * gpmc_fclk (14) if ((advrdofftime C clkactivationtime C 2) is a multiple of 3) for adv rising edge (adv deactivated) in writing mode: C case gpmcfclkdivider = 0: C g = 0.5 * advextradelay * gpmc_fclk (14) C case gpmcfclkdivider = 1: C g = 0.5 * advextradelay * gpmc_fclk (14) if (clkactivationtime and advwrofftime are odd) or (clkactivationtime and advwrofftime are even) C g = (1 + 0.5 * advextradelay) * gpmc_fclk (14) otherwise C case gpmcfclkdivider = 2: C g = 0.5 * advextradelay * gpmc_fclk (14) if ((advwrofftime C clkactivationtime) is a multiple of 3) C g = (1 + 0.5 * advextradelay) * gpmc_fclk (14) if ((advwrofftime C clkactivationtime C 1) is a multiple of 3) C g = (2 + 0.5 * advextradelay) * gpmc_fclk (14) if ((advwrofftime C clkactivationtime C 2) is a multiple of 3) (8) for oe falling edge (oe activated) / io dir rising edge (data bus input direction): C case gpmcfclkdivider = 0: o h = 0.5 * oeextradelay * gpmc_fclk (14) C case gpmcfclkdivider = 1: C h = 0.5 * oeextradelay * gpmc_fclk (14) if (clkactivationtime and oeontime are odd) or (clkactivationtime and oeontime are even) C h = (1 + 0.5 * oeextradelay) * gpmc_fclk (14) otherwise C case gpmcfclkdivider = 2: C h = 0.5 * oeextradelay * gpmc_fclk (14) if ((oeontime C clkactivationtime) is a multiple of 3) 162 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 C h = (1 + 0.5 * oeextradelay) * gpmc_fclk (14) if ((oeontime C clkactivationtime C 1) is a multiple of 3) C h = (2 + 0.5 * oeextradelay) * gpmc_fclk (14) if ((oeontime C clkactivationtime C 2) is a multiple of 3) for oe rising edge (oe deactivated): C case gpmcfclkdivider = 0: C h = 0.5 * oeextradelay * gpmc_fclk (14) C case gpmcfclkdivider = 1: C h = 0.5 * oeextradelay * gpmc_fclk (14) if (clkactivationtime and oeofftime are odd) or (clkactivationtime and oeofftime are even) C h = (1 + 0.5 * oeextradelay) * gpmc_fclk (14) otherwise C case gpmcfclkdivider = 2: C h = 0.5 * oeextradelay * gpmc_fclk (14) if ((oeofftime C clkactivationtime) is a multiple of 3) C h = (1 + 0.5 * oeextradelay) * gpmc_fclk (14) if ((oeofftime C clkactivationtime C 1) is a multiple of 3) C h = (2 + 0.5 * oeextradelay) * gpmc_fclk (14) if ((oeofftime C clkactivationtime C 2) is a multiple of 3) (9) for we falling edge (we activated): C case gpmcfclkdivider = 0: C i = 0.5 * weextradelay * gpmc_fclk (14) C case gpmcfclkdivider = 1: C i = 0.5 * weextradelay * gpmc_fclk (14) if (clkactivationtime and weontime are odd) or (clkactivationtime and weontime are even) C i = (1 + 0.5 * weextradelay) * gpmc_fclk (14) otherwise C case gpmcfclkdivider = 2: C i = 0.5 * weextradelay * gpmc_fclk (14) if ((weontime C clkactivationtime) is a multiple of 3) C i = (1 + 0.5 * weextradelay) * gpmc_fclk (14) if ((weontime C clkactivationtime C 1) is a multiple of 3) C i = (2 + 0.5 * weextradelay) * gpmc_fclk (14) if ((weontime C clkactivationtime C 2) is a multiple of 3) for we rising edge (we deactivated): C case gpmcfclkdivider = 0: C i = 0.5 * weextradelay * gpmc_fclk (14) C case gpmcfclkdivider = 1: C i = 0.5 * weextradelay * gpmc_fclk (14) if (clkactivationtime and weofftime are odd) or (clkactivationtime and weofftime are even) C i = (1 + 0.5 * weextradelay) * gpmc_fclk (14) otherwise C case gpmcfclkdivider = 2: C i = 0.5 * weextradelay * gpmc_fclk (14) if ((weofftime C clkactivationtime) is a multiple of 3) C i = (1 + 0.5 * weextradelay) * gpmc_fclk (14) if ((weofftime C clkactivationtime C 1) is a multiple of 3) C i = (2 + 0.5 * weextradelay) * gpmc_fclk (14) if ((weofftime C clkactivationtime C 2) is a multiple of 3) (10) j = gpmc_fclk (14) (11) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (12) p = gpmc_clk period in ns (13) for read: k = (advrdofftime C advontime) * (timeparagranularity + 1) * gpmc_fclk (14) for write: k = (advwrofftime C advontime) * (timeparagranularity + 1) * gpmc_fclk (14) (14) gpmc_fclk is general-purpose memory controller internal functional clock period in ns. (15) related to the gpmc_clk output clock maximum and minimum frequencies programmable in the gpmc module by setting the gpmc_config1_csx configuration register bit field gpmcfclkdivider. (16) the jitter probability density can be approximated by a gaussian function. (17) m = (rdcycletime C accesstime) * (timeparagranularity + 1) * gpmc_fclk (14) above m parameter expression is given as one example of gpmc programming. io dir signal will go from in to out after both rdcycletime and busturnaround completion. behavior of io direction signal does depend on kind of successive read/write accesses performed to memory and multiplexed or nonmultiplexed memory addressing scheme, bus keeping feature enabled or not. io dir behaviour is automatically handled by gpmc controller. for a full description of the gpmc_io_dir feature, see the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (18) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 163 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (2) in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-2. gpmc/nor flash synchronous single read (gpmcfclkdivider = 0) 164 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address d 0 out in out f0 f12 f13 f4 f6 f2 f8 f3 f7 f9 f11 f1 f1 f8 f19 f18 f20 f10 f6 f19 f23 f24 swps038-014
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (2) in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-3. gpmc/nor flash synchronous burst read 4x16-bit (gpmcfclkdivider = 0) copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 165 submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address d 0 d 1 d 2 out out in out f0 f12 f13 f13 f12 f4 f1 f1 f2 f6 f3 f7 f8 f8 f9 f10 f11 f21 f22 f6 f7 f23 f24 swps038-015 d 3
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (2) in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-4. gpmc/nor flash synchronous burst write (gpmcfclkdivider > 0) 166 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-016 gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir d 0 d 1 d 2 d 3 out f4 f15 f15 f15 f1 f1 f2 f6 f8 f8 f0 f14 f14 f3 f17 f17 f17 f9 f6 f17 f17 f17 valid address
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (2) in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-5. gpmc/multiplexed nor flash synchronous burst read copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 167 submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_clk gpmc_ncsx gpmc_nbe0_cle gpmc_nbe1 gpmc_a[27:17] (gpmc_a[11:1]) gpmc_a[16:1] (gpmc_d[15:0]) gpmc_nadv_ale gpmc_noe gpmc_waitx gpmc_io_dir valid valid address (msb) address (lsb) d0 d1 d2 d3 out out in out f4 f6 f4 f2 f8 f8 f10 f13 f12 f12 f11 f9 f7 f3 f0 f1 f1 f5 f6 f7 f23 f24 swps038-017
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (2) in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-6. gpmc/multiplexed nor flash synchronous burst write 168 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_clk gpmc_ncsx gpmc_a[27:17] (gpmc_a[11:1]) gpmc_nbe1 gpmc_nbe0_clegpmc_nadv_ale gpmc_nwe gpmc_waitx gpmc_io_dir address (lsb) d 0 d 1 d 2 d 3 out f4 f15 f15 f15 f1 f1 f2 f6 f8 f8 f0 f3 f17 f17 f17 f9 f6 f17 f17 f17 f18 f20 f14 f22 f21 swps038-018 address (msb) gpmc_a[16:1] (gpmc_d[15:0]) f14
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 6.4.1.2 gpmc/nor flash asynchronous mode table 6-6 and table 6-7 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-7 through figure 6-12 ). table 6-5. gpmc/nor flash timing conditions asynchronous mode timing condition parameter value unit input conditions t r input signal rise time 1.8 ns t f input signal fall time 1.8 ns output conditions c load output load capacitance (1) 16 pf (1) the load setting of the io buffer: lb0 = 0. table 6-6. gpmc/nor flash internal timing parameters asynchronous mode (1) (2) (4) no. parameter opp100 opp50 unit min max min max fi1 delay time, output data gpmc_d[15:0] generation from internal 6.6 7.0 ns functional clock gpmc_fclk (3) fi2 delay time, input data gpmc_d[15:0] capture from internal functional 4.4 7.0 ns clock gpmc_fclk (3) fi3 delay time, output chip select gpmc_ncsx generation from internal 6.5 7.0 ns functional clock gpmc_fclk (3) fi4 delay time, output address gpmc_a[27:1] generation from internal 7.6 7.0 ns functional clock gpmc_fclk (3) fi5 delay time, output address gpmc_a[27:1] valid from internal functional 7.6 7.0 ns clock gpmc_fclk (3) fi6 delay time, output lower-byte enable/command latch enable 6.5 7.0 ns gpmc_nbe0_cle, output upper-byte enable gpmc_nbe1 generation from internal functional clock gpmc_fclk (3) fi7 delay time, output enable gpmc_noe generation from internal 5.8 7.0 ns functional clock gpmc_fclk (3) fi8 delay time, output write enable gpmc_nwe generation from internal 7.0 7.0 ns functional clock gpmc_fclk (3) fi9 skew, internal functional clock gpmc_fclk (3) 100 170 ps fi10 delay time, io direction generation from internal functional clock 6.3 7.0 ps gpmc_fclk (3) (1) the internal parameters table must be used to calculate data access time stored in the corresponding cs register bit field. (2) internal parameters are referred to the gpmc functional internal clock which is not provided externally. (3) gpmc_fclk is general-purpose memory controller internal functional clock. (4) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 169 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-7. gpmc/nor flash timing requirements asynchronous mode (7) no. parameter opp100 opp50 unit min max min max fa5 (1) t acc(d) data access time h (5) h (5) ns fa20 (3) t acc1-pgmode(d) page mode successive data access time p (4) p (4) ns fa21 (2) t acc2-pgmode(d) page mode first data access time h (5) h (5) ns (1) the fa5 parameter illustrates the amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data is internally sampled by active functional clock edge. fa5 value must be stored inside the accesstime register bit field. (2) the fa21 parameter illustrates amount of time required to internally sample first input page data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa21 functional clock cycles, first input page data is internally sampled by active functional clock edge. fa21 value must be stored inside the accesstime register bit field. (3) the fa20 parameter illustrates amount of time required to internally sample successive input page data. it is expressed in number of gpmc functional clock cycles. after each access to input page data, next input page data is internally sampled by active functional clock edge after fa20 functional clock cycles. the fa20 value must be stored in the pageburstaccesstime register bit field. (4) p = pageburstaccesstime * (timeparagranularity + 1) * gpmc_fclk (6) (5) h = accesstime * (timeparagranularity + 1) * gpmc_fclk (6) (6) gpmc_fclk is general-purpose memory controller internal functional clock period in ns. (7) see section 4.3.4 , processor clocks . table 6-8. gpmc/nor flash switching characteristics asynchronous mode (16) no. parameter opp100 opp50 unit min max min max t r(d) rise time, output data gpmc_d[15:0] 2 2 ns t f(d) fall time, output data gpmc_d[15:0] 2 2 ns fa0 t w(nbev) pulse duration, output lower-byte read n (12) n (12) ns enable/command latch enable write n (12) n (12) gpmc_nbe0_cle, output upper-byte enable gpmc_nbe1 valid time fa1 t w(ncsv) pulse duration, output chip select read a (1) a (1) ns gpmc_ncsx (13) low write a (1) a (1) fa3 t d(ncsv-nadviv) delay time, output chip select read b (2) C 0.2 b (2) + 2.0 b (2) C 0.2 b (2) + 2.6 ns gpmc_ncsx (13) valid to output write b (2) C 0.2 b (2) + 2.0 b (2) C 0.2 b (2) + 2.6 address valid/address latch enable gpmc_nadv_ale invalid fa4 t d(ncsv-noeiv) delay time, output chip select gpmc_ncsx (13) c (3) C 0.2 c (3) + 2.0 c (3) C 0.2 c (3) + 2.6 ns valid to output enable gpmc_noe invalid (single read) fa9 t d(av-ncsv) delay time, output address gpmc_a[27:1] valid j (9) C 0.2 j (9) + 2.0 j (9) C 0.2 j (9) + 2.6 ns to output chip select gpmc_ncsx (13) valid fa10 t d(nbev-ncsv) delay time, output lower-byte j (9) C 0.2 j (9) + 2.0 j (9) C 0.2 j (9) + 2.6 ns enable/command latch enable gpmc_nbe0_cle, output upper-byte enable gpmc_nbe1 valid to output chip select gpmc_ncsx (13) valid fa12 t d(ncsv-nadvv) delay time, output chip select gpmc_ncsx (13) k (10) C 0.2 k (10) + 2.0 k (10) C 0.2 k (10) + 2.6 ns valid to output address valid/address latch enable gpmc_nadv_ale valid fa13 t d(ncsv-noev) delay time, output chip select gpmc_ncsx (13) l (11) C 0.2 l (11) + 2.0 l (11) C 0.2 l (11) + 2.6 ns valid to output enable gpmc_noe valid fa14 t d(ncsv-iodir) delay time, output chip select gpmc_ncsx (13) l (11) C 0.2 l (11) + 2.0 l (11) C 0.2 l (11) + 2.6 ns valid to output io direction control gpmc_io_dir high fa15 t d(ncsv-iodir) delay time, output chip select gpmc_ncsx (13) m (14) C 0.2 m (14) + 2.0 m (14) C 0.2 m (14) + 2.6 ns valid to output io direction control gpmc_io_dir low 170 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-8. gpmc/nor flash switching characteristics asynchronous mode (16) (continued) no. parameter opp100 opp50 unit min max min max fa16 t w(aiv) pulse durationm output address gpmc_a[26:1] g (7) g (7) ns invalid between 2 successive r/w accesses fa18 t d(ncsv-noeiv) delay time, output chip select gpmc_ncsx (13) i (8) C 0.2 i (8) + 2.0 i (8) C 0.2 i (8) + 2.6 ns valid to output enable gpmc_noe invalid (burst read) fa20 t w(av) pulse duration, output address gpmc_a[27:1] d (4) d (4) ns valid C 2nd, 3rd, and 4th accesses fa25 t d(ncsv-nwev) delay time, output chip select gpmc_ncsx (13) e (5) C 0.2 e (5) + 2.0 e (5) C 0.2 e (5) + 2.6 ns valid to output write enable gpmc_nwe valid fa27 t d(ncsv-nweiv) delay time, output chip select gpmc_ncsx (13) f (6) C 0.2 f (6) + 2.0 f (6) C 0.2 f (6) + 2.6 ns valid to output write enable gpmc_nwe invalid fa28 t d(nwev-dv) delay time, output write enable gpmc_ nwe 2.0 2.6 ns valid to output data gpmc_d[15:0] valid fa29 t d(dv-ncsv) delay time, output data gpmc_d[15:0] valid to j (9) C 0.2 j (9) + 2.0 j (9) C 0.2 j (9) + 2.6 ns output chip select gpmc_ncsx (13) valid fa37 t d(noev-aiv) delay time, output enable gpmc_noe valid to 2.0 2.6 ns output address gpmc_a[16:1]_d[15:0] phase end (1) for single read: a = (csrdofftime C csontime) * (timeparagranularity + 1) * gpmc_fclk (15) for single write: a = (cswrofftime C csontime) * (timeparagranularity + 1) * gpmc_fclk (15) for burst read: a = (csrdofftime C csontime + (n C 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (15) for burst write: a = (cswrofftime C csontime + (n C 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (15) with n being the page burst access number (2) for reading: b = ((advrdofftime C csontime) * (timeparagranularity + 1) + 0.5 * (advextradelay C csextradelay)) * gpmc_fclk (15) for writing: b = ((advwrofftime C csontime) * (timeparagranularity + 1) + 0.5 * (advextradelay C csextradelay)) * gpmc_fclk (15) (3) c = ((oeofftime C csontime) * (timeparagranularity + 1) + 0.5 * (oeextradelay C csextradelay)) * gpmc_fclk (15) (4) d = pageburstaccesstime * (timeparagranularity + 1) * gpmc_fclk (15) (5) e = ((weontime C csontime) * (timeparagranularity + 1) + 0.5 * (weextradelay C csextradelay)) * gpmc_fclk (15) (6) f = ((weofftime C csontime) * (timeparagranularity + 1) + 0.5 * (weextradelay C csextradelay)) * gpmc_fclk (15) (7) g = cycle2cycledelay * gpmc_fclk (15) (8) i = ((oeofftime + (n C 1) * pageburstaccesstime C csontime) * (timeparagranularity + 1) + 0.5 * (oeextradelay C csextradelay)) * gpmc_fclk (15) (9) j = (csontime * (timeparagranularity + 1) + 0.5 * csextradelay) * gpmc_fclk (15) (10) k = ((advontime C csontime) * (timeparagranularity + 1) + 0.5 * (advextradelay C csextradelay)) * gpmc_fclk (15) (11) l = ((oeontime C csontime) * (timeparagranularity + 1) + 0.5 * (oeextradelay C csextradelay)) * gpmc_fclk (15) (12) for single read: n = rdcycletime * (timeparagranularity + 1) * gpmc_fclk (15) for single write: n = wrcycletime * (timeparagranularity + 1) * gpmc_fclk (15) for burst read: n = (rdcycletime + (n C 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (15) for burst write: n = (wrcycletime + (n C 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (15) (13) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (14) m = ((rdcycletime C csontime) * (timeparagranularity + 1) C 0.5 * csextradelay) * gpmc_fclk (15) above m parameter expression is given as one example of gpmc programming. io dir signal will go from in to out after both rdcycletime and busturnaround completion. behavior of io direction signal does depend on kind of successive read/write accesses performed to memory and multiplexed or nonmultiplexed memory addressing scheme, bus keeping feature enabled or not. io dir behaviour is automatically handled by gpmc controller. for a full description of the gpmc_io_dir feature, see the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (15) gpmc_fclk is general-purpose memory controller internal functional clock period in ns. (16) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 171 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data will be internally sampled by active functional clock edge. fa5 value must be stored inside accesstime register bits field. (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. figure 6-7. gpmc / nor flash asynchronous read single word 172 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address valid valid data in 0 data in 0 out in out fa0 fa9 fa10 fa3 fa1 fa4 fa12 fa13 fa0 fa10 fa5 fa14 fa15 swps038-019
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data will be internally sampled by active functional clock edge. fa5 value must be stored inside accesstime register bits field. (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. figure 6-8. gpmc / nor flash asynchronous read 32-bit copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 173 submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir address 0 address 1 valid valid valid valid data upper out in out in fa9 fa10 fa3 fa9 fa3 fa13 fa13 fa1 fa1 fa4 fa4 fa12 fa12 fa10 fa0 fa0 fa16 fa0 fa0 fa10 fa10 fa5 fa5 fa14 fa15 fa14 fa15 swps038-020
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) fa21 parameter illustrates amount of time required to internally sample first input page data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. fa21 calculation must be stored inside accesstime register bits field. (3) fa20 parameter illustrates amount of time required to internally sample successive input page data. it is expressed in number of gpmc functional clock cycles. after each access to input page data, next input page data will be internally sampled by active functional clock edge after fa20 functional clock cycles. fa20 is also the duration of address phases for successive input page data (excluding first input page data). fa20 value must be stored in pageburstaccesstime register bits field. (4) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. figure 6-9. gpmc / nor flash asynchronous read page mode 4x16-bit 174 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir add0 add1 add2 add3 add4 d0 d1 d2 d3 d3 out in out fa1 fa0 fa18 fa13 fa12 fa0 fa9 fa10 fa10 fa21 fa14 fa15 swps038-021 fa20 fa20 fa20
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-10. gpmc / nor flash asynchronous write single word copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 175 submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address data out out fa0 fa1 fa10 fa3 fa25 fa29 fa9 fa12 fa27 fa0 fa10 swps038-022
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data will be internally sampled by active functional clock edge. fa5 value must be stored inside accesstime register bits field. (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. figure 6-11. gpmc / multiplexed nor flash asynchronous read single word 176 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_fclk gpmc_clk gpmc_ncsx gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_io_dir gpmc_waitx address (msb) valid valid address (lsb) data in data in out in out fa0 fa9 fa10 fa3 fa13 fa29 fa1 fa37 fa12 fa4 fa10 fa0 fa5 fa14 fa15 swps038-023 gpmc_a[27:17] (gpmc_a[11:1]) gpmc_a[16:1] (gpmc_d[15:0])
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-12. gpmc / multiplexed nor flash asynchronous write single word copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 177 submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[27:17] (gpmc_a[11:1]) gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_a[16:1] (gpmc_d[15:0]) gpmc_waitx gpmc_io_dir address (msb) valid address (lsb) data out out fa0 fa1 fa9 fa10 fa3 fa25 fa29 fa12 fa27 fa28 fa0 fa10 swps038-024
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.4.1.3 gpmc/nand flash asynchronous mode table 6-10 and table 6-11 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-13 through figure 6-16 ). table 6-9. gpmc/nand flash timing conditions asynchronous mode timing condition parameter value unit input conditions t r input signal rise time 1.8 ns t f input signal fall time 1.8 ns output conditions c load output load capacitance (1) 16 pf (1) the load setting of the io buffer: lb0 = 0. table 6-10. gpmc/nand flash internal timing parameters asynchronous mode (1) (2) (4) no. parameter opp100 opp50 unit min max min max gnfi1 delay time, output data gpmc_d[15:0] generation from internal 6.5 9.1 ns functional clock gpmc_fclk (3) gnfi2 delay time, input data gpmc_d[15:0] capture from internal 4.0 5.6 ns functional clock gpmc_fclk (3) gnfi3 delay time, output chip select gpmc_ncsx generation from 6.5 9.1 ns internal functional clock gpmc_fclk (3) gnfi4 delay time, output address valid/address latch enable 6.5 9.1 ns gpmc_nadv_ale generation from internal functional clock gpmc_fclk (3) gnfi5 delay time, output lower-byte enable/command latch enable 6.5 9.1 ns gpmc_nbe0_cle generation from internal functional clock gpmc_fclk (3) gnfi6 delay time, output enable gpmc_noe generation from internal 6.5 9.1 ns functional clock gpmc_fclk (3) gnfi7 delay time, output write enable gpmc_nwe generation from 6.5 9.1 ns internal functional clock gpmc_fclk (3) gnfi8 skew, functional clock gpmc_fclk (3) 100 170 ps (1) internal parameters table must be used to calculate data access time stored in the corresponding cs register bit field. (2) internal parameters are referred to the gpmc functional internal clock which is not provided externally. (3) gpmc_fclk is general-purpose memory controller internal functional clock. (4) see section 4.3.4 , processor clocks . table 6-11. gpmc/nand flash timing requirements asynchronous mode (4) no. parameter opp100 opp50 unit min max min max gnf12 (1) t acc(d) access time, input data gpmc_d[15:0] j (2) j (2) ns (1) the gnf12 parameter illustrates the amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of the read cycle and after gnf12 functional clock cycles, input data is internally sampled by the active functional clock edge. the gnf12 value must be stored inside accesstime register bit field. (2) j = accesstime * (timeparagranularity + 1) * gpmc_fclk (3) (3) gpmc_fclk is general-purpose memory controller internal functional clock period in ns. (4) see section 4.3.4 , processor clocks . 178 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-12. gpmc/nand flash switching characteristics asynchronous mode (15) no. parameter opp100 opp50 unit min max min max t r(d) rise time, output data gpmc_d[15:0] 2 2 ns t f(d) fall time, output data gpmc_d[15:0] 2 2 ns gnf0 t w(nwev) pulse duration, output write enable gpmc_nwe a (1) a (1) ns valid gnf1 t d(ncsv-nwev) delay time, output chip select gpmc_ncsx (13) b (2) C 0.2 b (2) + 2.0 b (2) C 0.2 b (2) + 2.6 ns valid to output write enable gpmc_nwe valid gnf2 t w(cleh-nwev) delay time, output lower-byte c (3) C 0.2 c (3) + 2.0 c (3) C 0.2 c (3) + 2.6 ns enable/command latch enable gpmc_nbe0_cle high to output write enable gpmc_nwe valid gnf3 t w(nwev-dv) delay time, output data gpmc_d[15:0] valid to d (4) C 0.2 d (4) + 2.0 d (4) C 0.2 d (4) + 2.6 ns output write enable gpmc_nwe valid gnf4 t w(nweiv-div) delay time, output write enable gpmc_nwe e (5) C 0.2 e (5) + 2.0 e (5) C 0.2 e (5) + 2.6 ns invalid to output data gpmc_d[15:0] invalid gnf5 t w(nweiv-cleiv) delay time, output write enable gpmc_nwe f (6) C 0.2 f (6) + 2.0 f (6) C 0.2 f (6) + 2.6 ns invalid to output lower-byte enable/command latch enable gpmc_nbe0_cle invalid gnf6 t w(nweiv-ncsiv) delay time, output write enable gpmc_nwe g (7) C 0.2 g (7) + 2.0 g (7) C 0.2 g (7) + 2.6 ns invalid to output chip select gpmc_ncsx (13) invalid gnf7 t w(aleh-nwev) delay time, output address valid/address latch c (3) C 0.2 c (3) + 2.0 c (3) C 0.2 c (3) + 2.6 ns enable gpmc_nadv_ale high to output write enable gpmc_nwe valid gnf8 t w(nweiv-aleiv) delay time, output write enable gpmc_nwe f (6) C 0.2 f (6) + 2.0 f (6) C 0.2 f (6) + 2.6 ns invalid to output address valid/address latch enable gpmc_nadv_ale invalid gnf9 t c(nwe) cycle time, write h (8) h (8) ns gnf10 t d(ncsv-noev) delay time, output chip select gpmc_ncsx (13) i (9) C 0.2 i (9) + 2.0 i (9) C 0.2 i (9) + 2.6 ns valid to output enable gpmc_noe valid gnf13 t w(noev) pulse duration, output enable gpmc_noe valid k (10) k (10) ns gnf14 t c(noe) cycle time, read l (11) l (11) ns gnf15 t w(noeiv-ncsiv) delay time, output enable gpmc_noe invalid to m (12) C 0.2 m (12) + 2.0 m (12) C 0.2 m (12) + 2.6 ns output chip select gpmc_ncsx (13) invalid (1) a = (weofftime C weontime) * (timeparagranularity + 1) * gpmc_fclk (14) (2) b = ((weontime C csontime) * (timeparagranularity + 1) + 0.5 * (weextradelay C csextradelay)) * gpmc_fclk (14) (3) c = ((weontime C advontime) * (timeparagranularity + 1) + 0.5 * (weextradelay C advextradelay)) * gpmc_fclk (14) (4) d = (weontime * (timeparagranularity + 1) + 0.5 * weextradelay) * gpmc_fclk (14) (5) e = ((wrcycletime C weofftime) * (timeparagranularity + 1) C 0.5 * weextradelay) * gpmc_fclk (14) (6) f = ((advwrofftime C weofftime) * (timeparagranularity + 1) + 0.5 * (advextradelay C weextradelay)) * gpmc_fclk (14) (7) g = ((cswrofftime C weofftime) * (timeparagranularity + 1) + 0.5 * (csextradelay C weextradelay)) * gpmc_fclk (14) (8) h = wrcycletime * (1 + timeparagranularity) * gpmc_fclk (14) (9) i = ((oeontime C csontime) * (timeparagranularity + 1) + 0.5 * (oeextradelay C csextradelay)) * gpmc_fclk (14) (10) k = (oeofftime C oeontime) * (1 + timeparagranularity) * gpmc_fclk (14) (11) l = rdcycletime * (1 + timeparagranularity) * gpmc_fclk (14) (12) m = ((csrdofftime C oeofftime) * (timeparagranularity + 1) + 0.5 * (csextradelay C oeextradelay)) * gpmc_fclk (14) (13) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (14) gpmc_fclk is general-purpose memory controller internal functional clock period in ns. (15) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 179 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. figure 6-13. gpmc / nand flash command latch cycle (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. figure 6-14. gpmc / nand flash address latch cycle 180 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_fclk gpmc_ncsx gpmc_nbe0_clegpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1] (gpmc_d[15:0]) command gnf0 gnf1 gnf2 gnf3 gnf4 gnf5 gnf6 swps038-025 gpmc_fclk gpmc_ncsx gpmc_nbe0_clegpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1] (gpmc_d[15:0]) address gnf0 gnf1 gnf7 gnf3 gnf4 gnf6 gnf8 gnf9 swps038-026
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) gnf12 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after gnf12 functional clock cycles, input data will be internally sampled by active functional clock edge. gnf12 value must be stored inside accesstime register bits field. (2) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. (3) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-15. gpmc / nand flash data read cycle (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. figure 6-16. gpmc / nand flash data write cycle copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 181 submit documentation feedback product folder link(s): dm3730 dm3725 gpmc_fclk gpmc_ncsx gpmc_nbe0_clegpmc_nadv_ale gpmc_noe gpmc_waitx data gnf10 gnf14 gnf15 gnf12 swps038-027 gnf13 gpmc_a[16:1] (gpmc_d[15:0]) gpmc_fclk gpmc_ncsx gpmc_nbe0_clegpmc_nadv_ale gpmc_noe gpmc_nwe data gnf0 gnf1 gnf4 gnf9 gnf3 gnf6 swps038-028 gpmc_a[16:1] (gpmc_d[15:0])
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.4.2 sdram memory controller (sdrc) note for more information, see memory subsystem / sdram controller (sdrc) subsystem section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the sdram controller subsystem module provides connectivity between the processor and external dram memory components. the module includes support for double-data-rate sdram (mobile ddr). 6.4.2.1 lpddr interface the lpddr interface is balled out on the bottom side of the cus package and on the top side of the pop packages. the lpddr interface on the top of the pop package has been designed for compatibility any pop lpddr device with a matching footprint and compliance with the jedec lpddr-266 specification. this section provides the timing specification for the bottom-side lpddr interface as a pcb design and manufacturing specification. the design rules constrain pcb trace length, pcb trace skew, signal integrity, cross-talk, and signal timing. these rules, when followed, result in a reliable lpddr memory system without the need for a complex timing closure process. for more information regarding guidelines for using this lpddr specification, see the understanding ti's pcb routing rule-based ddr timing specification application report (literature number spraav0 ). 6.4.2.1.1 lpddr interface schematic figure 6-17 and figure 6-18 show the lpddr interface schematics for a lpddr memory system. the 1 x16 lpddr system schematic is identical to figure 6-17 except that the high word lpddr device is deleted. 182 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 6-17. dm37x lpddr high level schematic (x16 memories) copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 183 submit documentation feedback product folder link(s): dm3730 dm3725 sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1 sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0sdrc_ncs1 n/c sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0sdrc_cke1 n/c sdrc_clk sdrc_nclk t t t t t t t t t t t t t t t t t t t dq0dq7 ldm ldqs dq8 dq15 udm udqs ba0 ba1 a0 a14 cs cas ras we ckeck ck ba0ba1 a0 a14 cs cas ras we ckeck ck t t t t t t t t lpddr dq0dq7 ldm ldqs dq8 dq15udm udqs lpddr
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 6-18. dm37x lpddr high level schematic (x32 memory) 6.4.2.1.2 compatible jedec lpddr devices table 6-13 shows the parameters of the jedec lpddr devices that are compatible with this interface. generally, the lpddr interface is compatible with x16 and x32 lpddr266 and lpddr333 speed grade lpddr devices. table 6-13. compatible jedec lpddr devices no. parameter min max unit notes jedec lpddr device speed 1 lpddr-266 see note (1) grade 2 jedec lpddr device bit width 16 32 bits 3 jedec lpddr device count 1 2 devices see note (2) jedec lpddr device ball 4 60 90 balls count 184 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1 sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_clk sdrc_nclk t t t t t t t t t t t t t t t t t t t ba0ba1 a0 a14 cs cas ras we ckeck ck t t t t t t t t dq0dq7 dm0 dqs0 dq8 dq15dm1 dqs1 lpddr dq16dq23 dm2 dqs2 dq24 dq31 dm3 dqs3 n/c n/c sdrc_ncs1 sdrc_cke1
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) higher lpddr speed grades are supported due to inherent jedec lpddr backwards compatibility. (2) 1 x16 lpddr device is used for 16 bit lpddr memory system. 1x32 or 2x16 lpddr devices are used for a 32-bit lpddr memory system. 6.4.2.1.3 pcb stackup the minimum stackup required for routing the dm37x is a six layer stack as shown in table 6-14 . additional layers may be added to the pcb stack up to accommodate other circuitry or to reduce the size of the pcb footprint. table 6-14. dm37x minimum pcb stack up layer type description 1 signal top routing mostly horizontal 2 plane ground 3 plane power 4 signal internal routing 5 plane ground 6 signal bottom routing mostly vertical table 6-15. pcb stack up specifications (4) no. parameter min typ max unit notes 1 pcb routing/plane layers 6 2 signal routing layers 3 3 full ground layers under lpddr routing region 2 4 number of ground plane cuts allowed within lpddr routing region 0 number of ground reference planes required for each lpddr routing 1 5 1 layer number of layers between lpddr routing layer and reference ground 0 6 0 plane 7 pcb routing feature size 4 mils 8 pcb trace width w 4 mils 9 pcb bga escape via pad size 18 mils 10 pcb bga escape via hole size 8 mils 11 device bga pad size see note (1) 12 lpddr device bga pad size see note (2) 13 single ended impedance, zo 50 75 ? 14 impedance control z-5 z z + 5 ? see note (3) (1) see the flip chip ball grid array package (spru811) reference guide for device bga pad size. (2) see the lpddr device manufacturer documentation for the lpddr device bga pad size. (3) z is the nominal singled ended impedance selected for the pcb specified by item 12. (4) specific routing guidelines for the cus package can be found in the am37x cus routing guidelines (sprabd4) application note. 6.4.2.2 placement figure 6-19 shows the required placement for the dm37x device as well as the lpddr devices. the dimensions for figure 6-19 are defined in table 6-16 . the placement does not restrict the side of the pcb that the devices are mounted on. the ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. for 1x16 and 1x32 lpddr memory systems, the second lpddr device is omitted from the placement. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 185 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 6-19. dm37xx and lpddr device placement table 6-16. placement specifications no. parameter min max unit notes 1 x 1440 mils see notes (1) , (2) 2 y 1030 mils see notes (1) , (2) 3 y offset 525 mils see notes (1) , (2) , (3) 4 lpddr keepout region see note (4) clearance from non-lpddr signal to lpddr 5 4 w see note (5) keepout region (1) see figure 6-17 for dimension definitions. (2) measurements from center of device to center of lpddr device. (3) for 16 bit memory systems it is recommended that y offset be as small as possible. (4) lpddr keepout region to encompass entire lpddr routing area. (5) non-lpddr signals allowed within lpddr keepout region provided they are separated from lpddr routing layers by a ground plane. 6.4.2.3 lpddr keep out region the region of the pcb used for the lpddr circuitry must be isolated from other signals. the lpddr keep out region is defined for this purpose and is shown in figure 6-20 . the size of this region varies with the placement and lpddr routing. additional clearances required for the keep out region are shown in table 6-16 . 186 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 a1a1 x y offset recommended lpddr device orientation y y offset lpddr device lpddr controller omap
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 6-20. lpddr keepout region 6.4.2.4 net classes table 6-17 lists the clock net classes for the lpddr interface. table 6-18 lists the signal net classes, and associated clock net classes, for the signals in the lpddr interface. these net classes are used for the termination and routing rules that follow. table 6-17. clock net class definitions clock net class pin names ck sdrc_clk/sdrc_nclk dqs0 sdrc_dqs0 dqs1 sdrc_dqs1 dqs2 sdrc_dqs2 dqs3 sdrc_dqs3 table 6-18. signal net class definitions clock net class associated clock net class pin names sdrc_ba[1:0], sdrc_a[14:0], sdrc_ncs[1:0], addr_ctrl ck sdrc_ncas, sdrc_nras, sdrc_nwe, sdrc_cke[1:0] dq0 dqs0 sdrc_d[7:0], sdrc_dm0 dq1 dqs1 sdrc_d[15:8], sdrc_dm1 dq2 dqs2 sdrc_d[23:16], sdrc_dm2 dq3 dqs3 sdrc_d[31:24], sdrc_dm3 6.4.2.5 lpddr signal termination no terminations of any kind are required in order to meet signal integrity and overshoot requirements. serial terminators are permitted, if desired, to reduce emi risk; however, serial terminations are the only type permitted. table 6-19 shows the specifications for the series terminators. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 187 submit documentation feedback product folder link(s): dm3730 dm3725 a1a1 lpddr controller lpddr device region should encompass all lpddr circuitry and varies dependingon placement. non-lpddr signals should not be routed on the lpddr signal layers within the lpddr keep out region. non-lpddr signals may be routed in the region provided they are routed on layers separated from lpddr signal layers by a ground layer. no breaks should be allowed in the reference ground layers in this region. in addition, the 1.8 v power plane should cover the entire keep out region.
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-19. lpddr signal terminations no. parameter min typ max unit notes 1 ck net class 0 10 ? see note (1) 2 addr_ctrl net class 0 22 zo ? see notes (1) , (2) , (3) data byte net classes 3 0 22 zo ? see notes (1) , (2) , (3) (dqs0-dqs3, dq0-dq3) (1) only series termination is permitted, parallel or sst specifically disallowed. (2) terminator values larger than typical only recommended to address emi issues. (3) termination value should be uniform across net class. 6.4.2.6 lpddr ck and addr_ctrl routing figure 6-21 shows the topology of the routing for the ck and addr_ctrl net classes. the route is a balanced t as it is intended that the length of segments b and c be equal. in addition, the length of a should be maximized. figure 6-21. ck and addr_ctrl routing and topology table 6-20. ck and addr_ctrl routing specification (5) no. parameter min typ max unit notes 1 center to center ck-ck spacing 2w 2 ck differential pair skew length mismatch (4) 25 mils see note (1) 3 ck b to c skew length mismatch 25 mils center to center ck to other 4 4w see note (2) lpddr trace spacing 5 ck/addr_ctrl nominal trace length caclm-50 caclm caclm+50 mils see note (3) 6 addr_ctrl to ck skew length mismatch 100 mils addr_ctrl to addr_ctrl 7 100 mils skew length mismatch center to center addr_ctrl to other 8 4w see note (2) lpddr trace spacing center to center addr_ctrl to other 9 3w see note (2) addr_ctrl trace spacing addr_ctrl a to b, addr_ctrl a to c 10 100 mils see note (1) skew length mismatch 11 addr_ctrl b to c skew length mismatch 100 mils (1) series terminator, if used, should be located closest to dm37x. (2) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (3) caclm is the longest manhattan distance of the ck and addr_ctrl net classes. (4) differential impedance should be 100 ohms. (5) specific routing guidelines for the cus package can be found in the am37x cus routing guidelines (sprabd4) application note. 188 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 a1 a1 c b a t lpddr controller omap
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 6-22 shows the topology and routing for the dqs and dq net classes; the routes are point to point. skew matching across bytes is not needed nor recommended. figure 6-22. dqs and dq routing and topology table 6-21. dqs and dq routing specification (1) (6) parameter min typ max unit notes dqs e skew length mismatch 25 mils center to center dqs to other lpddr trace 4w see note (2) spacing dqs/dq nominal trace length dqlm - 50 dqlm dqlm + 50 mils see note (2) dq to dqs skew length mismatch 100 mils see note (4) dq to dq skew length mismatch 100 mils see note (4) center to center dq to other lpddr trace 4w see note (5) spacing center to center dq to other dq trace 3w see note (2) , (3) spacing dq e skew length mismatch 100 mils (1) series terminator, if used, should be located closest to lpddr. (2) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (3) dqlm is the longest manhattan distance of the dqs and dq net classes. (4) there is no need, and it is not recommended, to skew match across data bytes. this specification is only relative within a data byte. (5) dqs from other bytes are considered other lpddr traces. (6) specific routing guidelines for the cus package can be found in the am37x cus routing guidelines (sprabd4) application note. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 189 submit documentation feedback product folder link(s): dm3730 dm3725 a1 a1 e0 t e1 t e2 omap e3 t lpddr controller t
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.5 multimedia interfaces 6.5.1 camera isp2p interface note for more information, see camera isp chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the camera subsystem provides the system interfaces and the processing capability to connect raw, yuv or jpeg image sensor modules to the device for video-preview, video-record and still-image-capture applications. the camera isp2p subsystem supports up to two simultaneous pixel flows but only one of them can use the video processing hardware: ? parallel camera interface + serial camera interface: one interface data goes through the video processing hardware. the other interface data goes directly to memory ? serial camera interface + serial camera interface: one serial interface data goes through the video processing hardware. the other serial interface data goes directly to memory. the camera isp2p subsystem supports different camera configurations: ? 10-bit parallel interface ? 12-bit parallel interface ? 12-bit parallel interface note : for more information, see the camera isp / camera isp environment / camera isp connectivity schemes section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). 6.5.1.1 camera output clocks (cam_xclka and cam_xclkb) table 6-22. isp2p cam_xclka and cam_xclkb output clocks switching characteristics no. parameter opp100 opp50 unit min max min max isp15 1 / t c(xclk) frequency (1) , output clock cam_xclkn (4) 216 216 mhz isp16 t w(xclkh) typical pulse duration, output clock 0.5p (2) 0.5p (2) ns cam_xclkn (4) high isp16 t w(xclkl) typical pulse duration, output clock 0.5p (2) 0.5p (2) ns cam_xclkn (4) low t dc(xclk) duty cycle error, output clock cam_xclkn (4) 0.5 * p (2) - 2.083 0.5 * p (2) - 2.083 ps t j(xclk) cycle jitter (3) , output clock cam_xclkn (4) 0.044 * p (2) 0.044 * p (2) ps t r(xclk) rise time, output clock cam_xclkn (4) 0.93 0.93 ns t f(xclk) fall time, output clock cam_xclkn (4) 0.93 0.93 ns (1) related with the cam_xclkn (4) maximum and minimum frequencies programmable in the isp module. note : you must disable the camera sensor or the camera module to change the frequency configuration. for more information, see the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (2) p = cam_xclkn (4) period in ns (3) maximum cycle jitter supported by cam_xclka and cam_xclkb output clocks. (4) in cam_xclkn, n is equal to a or b. 190 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 6.5.1.2 parallel camera interface (cpi) 6.5.1.2.1 cpi video and graphics digitizer 1.8v mode the imaging subsystem deals with the processing of the pixel data coming from an external image sensor or from video and graphics digitizer. it is a key component for the following multimedia applications: video preview, camera viewfinder, video record and still image capture. it supports raw, rgb, and yuv data processing. table 6-24 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-23 and figure 6-24 ). table 6-23. cpi timing conditions video and graphics digitizer 1.8-v mode timing condition parameter value unit min max input conditions t r input signal rise time 80 1800 ps t f input signal fall time 80 1800 ps table 6-24. cpi timing requirements video and graphics digitizer 1.8-v mode (4) (6) no. parameter opp100 unit min max isp1 1 / t c(pclk) frequency (1) , input pixel clock cam_pclk 148.5 mhz isp2 t w(pclkl) typical pulse duration, input pixel clock cam_pclk low 0.5p (2) ns isp3 t w(pclkh) typical pulse duration, input pixel clock cam_pclk high 0.5p (2) ns t dc(pclk) duty cycle error, input pixel clock cam_pclk 0.5*p (2) - ns 3.247 t j(pclk) cycle jitter (3) , input pixel clock cam_pclk 0.06p (2) ns isp4 t su(vsv-pclkh) setup time, input vertical synchronization cam_vs valid before input 0.75 ns pixel clock cam_pclk rising/falling edge isp5 t h(pclkh-vsv) hold time, input vertical synchronization cam_vs valid after input pixel 0.96 ns clock cam_pclk rising/falling edge isp6 t su(hsv-pclkh) setup time, input horizontal synchronization cam_hs valid before input 0.75 ns pixel clock cam_pclk rising/falling edge isp7 t h(pclkh-hsv) hold time, input horizontal synchronization cam_hs valid after input 0.96 ns pixel clock cam_pclk rising/falling edge isp8 t su(dv-pclkh) setup time, input data cam_d[n:0] (5) valid before input pixel clock 0.75 ns cam_pclk rising/falling edge isp9 t h(pclkh-dv) hold time, input data cam_d[n:0] (5) valid after input pixel clock 0.96 ns cam_pclk rising/falling edge isp10 t su(wenv-pclkh) setup time, input write enable cam_wen valid before input pixel clock 0.75 ns cam_pclk rising/falling edge isp11 t h(pclkh-wenv) hold time, input write enable cam_wen valid after input pixel clock 0.96 ns cam_pclk rising/falling edge isp12 t su(fldv-pclkh) setup time, input field identification cam_fld valid before input pixel 0.75 ns clock cam_pclk rising/falling edge isp13 t h(pclkh-fldv) hold time, input field identification cam_fld valid after input pixel clock 0.96 ns cam_pclk rising/falling edge (1) related with the input maximum frequency supported by the isp module in 8-bit mode with 8 to 16 data bits conversion bridge enabled. (2) p = cam_pclk period in ns (3) maximum cycle jitter supported by cam_pclk input clock (4) the timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. (5) n = 11 (data bus size is limited to 8 bits. so the bits configuration is either cam_d[7:0] or cam_d[11:4]). lines not connected must be tied low. (6) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 191 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. optionally, the cam_wen signal can be used as an external memory write-enable signal. for further details, see the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (2) n = 11 (data bus size is limited to 8 bits. so the bits configuration is either cam_d[7:0] or cam_d[11:4]). when the number of data lines is less than cam_d[n:0], data lines can be connected to the upper or lower lines of cam_d[n:0]. lines not connected must be tied low. for more information about video port mapping, see the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). figure 6-23. cpi video and graphics digitizer 1.8-v progressive mode 192 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 d(n-2) cam_pclk cam_vs cam_hs cam_d[n:0] cam_wen cam_fld d(0) d(n-2) d(n-1) d(0) d(n-1) isp1 isp4 isp5 isp6 isp7 isp9 isp8 isp10 isp11 isp3 swps038-048 isp2
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. optionally, the cam_wen signal can be used as an external memory write-enable signal. for further details, see the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (2) n = 11 (data bus size is limited to 8 bits. so the bits configuration is either cam_d[7:0] or cam_d[11:4]). when the number of data lines is less than cam_d[n:0], data lines can be connected to the upper or lower lines of cam_d[n:0]. lines not connected must be tied low. for more information about video port mapping, see the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). figure 6-24. cpi video and graphics digitizer 1.8-v interlaced mode 6.5.1.2.2 cpi 12-bit sync normal progressive mode table 6-26 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-25 ). table 6-25. cpi timing conditions 12-bit sync normal progressive mode (1) timing condition parameter value unit input conditions t r input signal rise time 2.7 ns t f input signal fall time 2.7 ns output condition c load output load capacitance 8.6 pf (1) the load setting of the io buffer: lb0 = 1. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 193 submit documentation feedback product folder link(s): dm3730 dm3725 cam_pclk cam_vs cam_hs cam_d[n:0] cam_wen cam_fld d(nC1) d(0) d(nC1) d(0) d(nC1) even odd isp1 isp2 isp4 isp5 isp6 isp7 isp9 isp8 isp10 isp11 isp3 isp12 isp13 swps038-049 d(0) d(0) d(nC1)
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-26. cpi timing requirements 12-bit sync normal progressive mode (4) (5) no. parameter opp100 opp50 unit min max min max isp17 1 / t c(pclk) frequency (1) , input pixel clock cam_pclk 75 45 mhz isp18 t w(pclkh) typical pulse duration, input pixel clock cam_pclk high 0.5p (2) 0.5p (2) ns isp18 t w(pclkl) typical pulse duration, input pixel clock cam_pclk low 0.5p (2) 0.5p (2) ns t dc(pclk) duty cycle error, input pixel clock cam_pclk 0.5p (2) - 0.5p (2) - ns 3.465 6.93 t j(pclk) cycle jitter (3) , input pixel clock cam_pclk 0.0649*p 0.0649*p ns (2) (2) isp19 t su(dv-pclkh) setup time, input data cam_d[11:0] valid before input 1.82 3.25 ns pixel clock cam_pclk rising edge isp20 t h(pclkh-dv) hold time, input data cam_d[11:0] valid after input 1.82 3.25 ns pixel clock cam_pclk rising edge isp21 t su(dv-vsh) setup time, input vertical synchronization cam_vs valid 1.82 3.25 ns before input pixel clock cam_pclk rising edge isp22 t h(pclkh-vsv) hold time, input vertical synchronization cam_vs valid 1.82 3.25 ns after input pixel clock cam_pclk rising edge isp23 t su(dv-hsh) setup time, input horizontal synchronization cam_hs 1.82 3.25 ns valid before input pixel clock cam_pclk rising edge isp24 t h(pclkh-hsv) hold time, input horizontal synchronization cam_hs 1.82 3.25 ns valid after input pixel clock cam_pclk rising edge isp25 t su(dv-hsh) setup time, input write enable cam_wen valid before 1.82 3.25 ns input pixel clock cam_pclk rising edge isp26 t h(pclkh-hsv) hold time, input write enable cam_wen valid after input 1.82 3.25 ns pixel clock cam_pclk rising edge (1) related with the input maximum frequency supported by the isp module. (2) p = cam_pclk period in ns (3) maximum cycle jitter supported by cam_pclk input clock. (4) the timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. (5) see section 4.3.4 , processor clocks . 194 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. if the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set. (2) the parallel camera in sync mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data. (3) when the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be grounded. (4) however, it is possible to shift the data to 0, 2, or 4 data internal lanes. (5) the bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode and cam_d[11:0] in 12-bit mode. (6) optionally, the data write to memory can be qualified by the external cam_wen signal. (7) the cam_wen signal can be used as an external memory write-enable signal. the data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (8) in cam_xclki, i can be equal to a or b. see table 6-22 for isp15 and isp16 parameters. figure 6-25. cpi 12-bit sync normal progressive mode 6.5.1.2.3 cpi 8-bit sync packed progressive mode table 6-28 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-26 ). table 6-27. cpi timing conditions 8-bit sync packed progressive mode (1) timing condition parameter value unit input conditions t r input signal rise time 2.5 ns t f input signal fall time 2.5 ns output condition c load output load capacitance 8.6 pf copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 195 submit documentation feedback product folder link(s): dm3730 dm3725 cam_xclki cam_pclk cam_vs cam_hs cam_d[11:0] cam_wen cam_fld d(0) d(nC3) d(nC2) d(nC1) d(0) d(1) isp15 isp16 isp16 isp17 isp18 isp19 isp20 isp21 isp22 isp24 isp23 isp25 isp26 isp18 swps038-050 d(nC1)
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) the load setting of the io buffer: lb0 = 1. table 6-28. cpi timing requirements 8-bit sync packed progressive mode (4) (5) no. parameter opp100 opp50 unit min max min max isp3 1 / t c(pclk) frequency (1) , input pixel clock cam_pclk 130 65 mhz isp4 t w(pclkh) typical pulse duration, input pixel clock 0.5*p (2) 0.5*p (2) ns cam_pclk high isp4 t w(pclkl) typical pulse duration, input pixel clock 0.5*p (2) 0.5*p (2) ns cam_pclk low t dc(pclk) duty cycle error, input pixel clock cam_pclk 0.5*p (2) - 0.5*p (2) - ns 3.465 6.93 t j(pclk) cycle jitter (3) , input pixel clock cam_pclk 0.0649*p (2) 0.0649*p (2) ns isp5 t su(dv-pclkh) setup time, input data cam_d[7:0] valid before 1.08 2.27 ns input pixel clock cam_pclk rising edge isp6 t h(pclkh-dv) hold time, input data cam_d[7:0] valid after input 1.08 2.27 ns pixel clock cam_pclk rising edge isp7 t su(dv-vsh) setup time, input vertical synchronization 1.08 2.27 ns cam_vs valid before input pixel clock cam_pclk rising edge isp8 t h(pclkh-vsv) hold time, input vertical synchronization cam_vs 1.08 2.27 ns valid after input pixel clock cam_pclk rising edge isp9 t su(dv-hsh) setup time, input horizontal synchronization 1.08 2.27 ns cam_hs valid before input pixel clock cam_pclk rising edge isp10 t h(pclkh-hsv) hold time, input horizontal synchronization 1.08 2.27 ns cam_hs valid after input pixel clock cam_pclk rising edge isp11 t su(dv-hsh) setup time, input write enable cam_wen valid 1.08 2.27 ns before input pixel clock cam_pclk rising edge isp12 t h(pclkh-hsv) hold time, input write enable cam_wen valid 1.08 2.27 ns after input pixel clock cam_pclk rising edge (1) related with the input maximum frequency supported by the isp module. (2) p = cam_pclk period in ns (3) maximum cycle jitter supported by cam_pclk input clock. (4) the timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. (5) see section 4.3.4 , processor clocks . 196 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. (2) the image sensor is connected to the lower data lines and the unused lines are grounded. however, it is possible to shift the data to 0, 2, or 4 data internal lanes. the bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode. (3) optionally, the data write to memory can be qualified by the external cam_wen signal. the cam_wen signal can be used as a external memory write-enable signal. the data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. the polarity of cam_fld is programmable. (4) the camera module can pack 8-bit data into 16 bits. it doubles the maximum pixel clock. this mode can be particularly useful to transfer an ycbcr data stream or compressed stream to memory at very high speed. (5) in cam_xclki, i can be equal to a or b. see table 6-22 for isp15 and isp16 parameters. figure 6-26. cpi 8-bit sync packed progressive mode 6.5.1.2.4 cpi 12-bit sync normal interlaced mode table 6-30 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-27 ). table 6-29. cpi timing conditions 12-bit sync normal interlaced mode timing condition parameter value unit input conditions t r input signal rise time 2.7 ns t f input signal fall time 2.7 ns output condition c load output load capacitance (1) 8.6 pf (1) the load setting of the io buffer: lb0 = 1. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 197 submit documentation feedback product folder link(s): dm3730 dm3725 cam_xclki cam_pclk cam_vs cam_hs cam_d[7:0] cam_wen cam_fld d(0) d(n-3) d(n-2) d(n-1) d(0) d(1) d(n-1) isp15 isp16 isp16 isp3 isp4 isp5 isp6 isp7 isp8 isp10 isp4 isp9 isp11 isp12 swps038-051
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-30. cpi timing requirements 12-bit sync normal interlaced mode (4) (5) no. parameter opp100 opp50 unit min max min max isp17 1 / t c(pclk) frequency (1) , input pixel clock cam_pclk 75 45 mhz isp18 t w(pclkh) typical pulse duration, input pixel clock cam_pclk high 0.5p (2) 0.5p (2) ns isp18 t w(pclkl) typical pulse duration, input pixel clock cam_pclk low 0.5p (2) 0.5p (2) ns t dc(pclk) duty cycle error, input pixel clock cam_pclk 0.5*p (2) - 0.5*p (2) - ns 3.465 6.93 t j(pclk) cycle jitter (3) , input pixel clock cam_pclk 0.0649*p 0.0649*p ns (2) (2) isp19 t su(dv-pclkh) setup time, input data cam_d[11:0] valid before input 1.82 3.25 ns pixel clock cam_pclk rising edge isp20 t h(pclkh-dv) hold time, input data cam_d[11:0] valid after input 1.82 3.25 ns pixel clock cam_pclk rising edge isp21 t su(dv-vsh) setup time, input vertical synchronization cam_vs valid 1.82 3.25 ns before input pixel clock cam_pclk rising edge isp22 t h(pclkh-vsv) hold time, input vertical synchronization cam_vs valid 1.82 3.25 ns after input pixel clock cam_pclk rising edge isp23 t su(dv-hsh) setup time, input horizontal synchronization cam_hs 1.82 3.25 ns valid before input pixel clock cam_pclk rising edge isp24 t h(pclkh-hsv) hold time, input horizontal synchronization cam_hs 1.82 3.25 ns valid after input pixel clock cam_pclk rising edge isp25 t su(dv-hsh) setup time, input write enable cam_wen valid before 1.82 3.25 ns input pixel clock cam_pclk rising edge isp26 t h(pclkh-hsv) hold time, input write enable cam_wen valid after input 1.82 3.25 ns pixel clock cam_pclk rising edge isp27 t su(dv-fldh) setup time, input field identification cam_fld valid 1.82 3.25 ns before input pixel clock cam_pclk rising edge isp28 t h(pclkh-fldv) hold time, input field identification cam_fld valid after 1.82 3.25 ns input pixel clock cam_pclk rising edge (1) related with the input maximum frequency supported by the isp module. (2) p = cam_pclk period in ns (3) maximum cycle jitter supported by cam_pclk input clock. (4) the timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. (5) see section 4.3.4 , processor clocks . 198 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. if the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set. (2) the parallel camera in sync mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data. (3) when the image sensor has fewer than 12 data lines, it is connected to the lower data lines and the unused lines are grounded. (4) it is possible to shift the data to 0, 2, or 4 data internal lanes. (5) the bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode and cam_d[11:0] in 12-bit mode. (6) optionally, the data write to memory can be qualified by the external cam_wen signal. (7) the cam_wen signal can be used as an external memory write-enable signal. the data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (8) in cam_xclki, i can be equal to a or b. see table 6-22 for isp15 and isp16 parameters. figure 6-27. cpi 12-bit sync normal interlaced mode section 5.3 copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 199 submit documentation feedback product folder link(s): dm3730 dm3725 cam_xclki cam_pclk cam_vs cam_hs cam_d[11:0] cam_wen cam_fld frame(0) l(0) l(0) d(0) d(n-3) d(n-2) d(n-1) d(0) d(1) d(2) d(n-1) pair impair isp16 isp16 isp17 isp18 isp27 isp19 isp21 isp22 isp23 isp20 isp28 isp25 isp26 swps038-052 frame(0) l(n-1) isp18 isp15 isp24
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.5.1.2.5 cpi 8-bit sync packed interlaced mode table 6-32 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-28 ). table 6-31. cpi timing conditions 8-bit sync packed interlaced mode timing condition parameter value unit input conditions t r input signal rise time 2.5 ns t f input signal fall time 2.5 ns output condition c load output load capacitance (1) 8.6 pf (1) the load setting of the io buffer: lb0 = 1. table 6-32. cpi timing requirements 8-bit sync packed interlaced mode (4) (5) no. parameter opp100 opp50 unit min max min max isp3 1 / t c(pclk) frequency (1) , input pixel clock cam_pclk 130 65 mhz isp4 t w(pclkh) typical pulse duration, input pixel clock cam_pclk high 0.5p (2) 0.5p (2) ns isp4 t w(pclkl) typical pulse duration, input pixel clock cam_pclk low 0.5p (2) 0.5p (2) ns t dc(pclk) duty cycle error, input pixel clock cam_pclk 0.5*p (2) - 0.5*p (2) - ns 3.465 6.93 t j(pclk) cycle jitter (3) , input pixel clock cam_pclk 0.0649*p 0.0649*p ns (2) (2) isp5 t su(dv-pclkh) setup time, input data cam_d[8:0] valid before input 1.08 2.27 ns pixel clock cam_pclk rising edge isp6 t h(pclkh-dv) hold time, input data cam_d[8:0] valid after input pixel 1.08 2.27 ns clock cam_pclk rising edge isp7 t su(dv-vsh) setup time, input vertical synchronization cam_vs valid 1.08 2.27 ns before input pixel clock cam_pclk rising edge isp8 t h(pclkh-vsv) hold time, input vertical synchronization cam_vs valid 1.08 2.27 ns after input pixel clock cam_pclk rising edge isp9 t su(dv-hsh) setup time, input horizontal synchronization cam_hs 1.08 2.27 ns valid before input pixel clock cam_pclk rising edge isp10 t h(pclkh-hsv) hold time, input horizontal synchronization cam_hs 1.08 2.27 ns valid after input pixel clock cam_pclk rising edge isp11 t su(dv-hsh) setup time, input write enable cam_wen valid before 1.08 2.27 ns input pixel clock cam_pclk rising edge isp12 t h(pclkh-hsv) hold time, input write enable cam_wen valid after input 1.08 2.27 ns pixel clock cam_pclk rising edge isp13 t su(dv-fldh) setup time, input field identification cam_fld valid 1.08 2.27 ns before input pixel clock cam_pclk rising edge isp14 t h(pclkh-fldv) hold time, input field identification cam_fld valid after 1.08 2.27 ns input pixel clock cam_pclk rising edge (1) related with the input maximum frequency supported by the isp module. (2) p = cam_pclk period in ns (3) maximum cycle jitter supported by cam_pclk input clock. (4) the timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. (5) see section 4.3.4 , processor clocks . 200 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. (2) the image sensor is connected to the lower data lines and the unused lines are grounded. however, it is possible to shift the data to 0, 2, or 4 data internal lanes. the bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode . (3) optionally, the data write to memory can be qualified by the external cam_wen signal. the cam_wen signal can be used as an external memory write-enable signal. the data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (4) the camera module can pack 8-bit data into 16 bits. it doubles the maximum pixel clock. this mode can be particularly useful to transfer a ycbcr data stream or compressed stream to memory at very high speed. (5) in cam_xclki, i can be equal to a or b. see table 6-22 for isp15 and isp16 parameters. figure 6-28. cpi 8-bit sync packed interlaced mode 6.5.1.2.6 cpi itu mode table 6-34 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-29 ). table 6-33. cpi timing conditions itu mode timing condition parameter value unit input conditions t r input signal rise time 2.7 ns t f input signal fall time 2.7 ns output condition c load output load capacitance (1) 8.6 pf (1) the load setting of the io buffer: lb0 = 1. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 201 submit documentation feedback product folder link(s): dm3730 dm3725 cam_xclki cam_pclk cam_vs cam_hs cam_d[7:0] cam_wen cam_fld frame(0) frame(0) l(0) l(0) d(0) d(n-3) d(n-2) d(0) d(1) d(2) d(n-1) pair impair isp15 isp16 isp16 isp3 isp4 isp4 isp13 isp5 isp7 isp8 isp9 isp6 isp14 isp11 isp12 swps038-053 d(n-1) l(n-1) isp10
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-34. cpi timing requirements itu mode (4) (5) no. parameter opp100 opp50 unit min max min max isp17 1 / t c(pclk) frequency (1) , input pixel clock cam_pclk 75 45 mhz isp18 t w(pclkh) typical pulse duration, input pixel clock cam_pclk high 0.5p (2) 0.5p (2) ns isp18 t w(pclkl) typical pulse duration, input pixel clock cam_pclk low 0.5p (2) 0.5p (2) ns t dc(pclk) duty cycle error, input pixel clock cam_pclk 0.5*p (2) - 0.5*p (2) - ns 3.465 6.93 t j(pclk) cycle jitter (3) , input pixel clock cam_pclk 0.0649*p 0.0649*p ns (2) (2) isp23 t su(dv-pclkh) setup time, input data cam_d[9:0] valid before input 1.82 3.25 ns pixel clock cam_pclk rising edge isp24 t h(pclkh-dv) hold time, input data cam_d[9:0] valid after input pixel 1.82 3.25 ns clock cam_pclk rising edge (1) related with the input maximum frequency supported by the isp module. (2) p = cam_pclk period in ns (3) maximum cycle jitter supported by cam_pclk input clock. (4) the timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. (5) see section 4.3.4 , processor clocks . (1) the unused lines are grounded and the data bus is connected to the lower data lines. however, it is possible to shift the data to 0, 2, or 4 data internal lanes. the different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in 10-bit mode. (2) the parallel camera in itu mode supports progressive camera modules. (3) in cam_xclki, i can be equal to a or b. see table 6-22 for isp15 and isp16 parameters. figure 6-29. cpi itu mode 202 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-054 cam_xclki cam_pclk cam_d[9:0] sof d(0) d(n-1) eof sof d(0) d(n-1) eof isp16 isp16 isp17 isp23 isp24 isp18 isp18 isp15
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 6.5.2 display subsystem (dss) note for more information, see display subsystem chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the display subsystem (dss) provides the logic to display the video frame from external (sdram) or internal (sram) memory on an lcd panel or a tv set. the display subsystem integrates the following elements: ? display controller (dispc) module ? remote frame buffer interface (rfbi) module ? ntsc/pal video encoder ? lcd display with: C parallel interface the two display supports can be active at the same time. 6.5.2.1 dss parallel interface in parallel interface, the paths of the display subsystem modules are the display controller and the rfbi. the display controller has two i/o pad modes and could be in the following configuration: ? bypass mode (rfbi disabled), which implements the mipi dpi protocol ? rfbi mode (rfbi enabled), which implements mipi dbi 2.0 type b protocol for more information about mipi dpi and mipi dbi protocols, see the dss chapter in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). 6.5.2.1.1 dss parallel interface bypass mode two types of lcd panel are supported: ? thin film transistor (tft) or active matrix technology ? supertwisted nematic (stn) or passive matrix technology both configurations are discussed in the following paragraphs. 6.5.2.1.2 dss parallel interface bypass mode tft mode table 6-36 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-30 ). table 6-35. dss timing conditions tft mode timing condition parameter value unit min max output condition c load output load capacitance (1) 10 pf (1) buffer strength configuration: lb0 = 1 table 6-36. dss switching characteristics tft mode (4) no. parameter opp100 opp50 unit min max min max dl0 t d(pclka-hsync) delay time, output pixel clock dss_pclk active edge to C 4.215 4.215 C 4.658 4.658 ns output horizontal synchronization dss_hsync transition dl1 t d(pclka-vsync) delay time, output pixel clock dss_pclk active edge to C 4.215 4.215 C 4.658 4.658 ns output vertical synchronization dss_vsync transition copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 203 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-36. dss switching characteristics tft mode (4) (continued) no. parameter opp100 opp50 unit min max min max dl2 t d(pclka-acbiasa) delay time, output pixel clock dss_pclk active edge to C 4.215 4.215 C 4.658 4.658 ns output data enable dss_acbias active level dl3 t d(pclka-dv) delay time, output pixel clock dss_pclk active edge to C 4.215 4.215 C 4.658 4.658 ns output data dss_data[23:0] valid dl4 1 / t c(pclk) frequency (2) , output pixel clock dss_pclk 74.3 (3) 66 (3) mhz dl5 t w(pclk) pulse duration, output pixel clock dss_pclk low or high 0.45p (1) 0.55p (1) 0.45p (1) 0.55p (1) ns (5) (5) (1) p = dss_pclk period in ns (2) the pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the dispc_divisor register. (3) for the dss (tft mode) in hd-tv application, to run at full speed (74.3 mhz) it is recommended to use the dss_data[5:0] signals on the dss_data[23:18] balls (h26, h25, e28, j26, ac27, ac28). in that case, the dss_data[23:18] signals are available on the sys_boot0, sys_boot1, sys_boot3, sys_boot4, sys_boot5, and sys_boot6 balls (ah26, ag26, af18, af19, ae21, af21) to run at full speed (74.3 mhz). if the dss_data[5:0] signals are used on the dss_data[5:0] balls (ag22, ah22, ag23, ah23, ag24, ah24), opp100 dss (tft mode) are limited at 66 mhz. the values may change following the silicon characterization result. (4) see section 4.3.4 , processor clocks . (5) tw(pclk) = 0.66.p when dispc_divisor[6:0] pcd = 3. (1) the pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins. (2) the pixel clock frequency is programmable. (3) all timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too. (4) for more information, see the dss chapter in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). figure 6-30. dss tft mode 6.5.2.1.3 dss parallel interface bypass mode stn mode table 6-38 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-31 ). table 6-37. dss timing conditions stn mode timing condition parameter value unit min max output condition c load output load capacitance (1) 40 pf 204 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-055 dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] dl4 dl5 dl3 dl0 dl2 dl1
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) buffer strength configuration: lb0 = 1 table 6-38. dss switching characteristics stn mode (3) (4) no. parameter opp100 opp50 unit min max min max dl3 t d(pclka-dv) delay time, output pixel clock dss_pclk active C 6.868 6.868 C 6.868 6.868 ns edge to output data dss_data[7:0] valid dl4 1 / t c(pclk) frequency (2) , output pixel clock dss_pclk 44 44 mhz dl5 t w(pclk) pulse duration, output pixel clock dss_pclk low 0.45p (1) 0.55p (1) (5) 0.45p (1) 0.55p (1) (5) ns or high (1) p = dss_pclk period in ns (2) the pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the dispc_divisor register. (3) the dss in stn mode is used with 4 or 8 pins only; unused pixel data bits always remain low. (4) see section 4.3.4 , processor clocks . (5) tw(pclk) = 0.66p when dispc_divisor[6:0] pcd = 3. (1) the pixel data bus depends on the use of 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins. (2) all timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too. (3) dss_vsync width must be programmed to be as small as possible. (4) the pixel clock frequency is programmable. (5) for more information, see the dss chapter in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). figure 6-31. dss stn mode 6.5.2.2 dss parallel interface rfbi mode applications 6.5.2.2.1 dss parallel interface rfbi mode mipi dbi-b 2.0 lcd panel the remote frame buffer interface (rfbi) module provides the necessary control signals and data (mipi ? dbi 2.0 type b protocol) to interface to the lcd driver of the lcd panel. table 6-40 and table 6-41 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-32 through figure 6-34 ). copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 205 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-056 dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] dl4 dl5 dl3
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-39. dss timing conditions rfbi mode mipi dbi 2.0 - lcd panel (2) timing condition parameter value unit min max input conditions t r input signal rise time 15 ns t f input signal fall time 15 ns output condition c load output load capacitance (1) 30 pf (1) buffer strength configuration: lb0 = 1. (2) for any information regarding the rfbi registers configuration, see display subsystem / the display subsystem environment / lcd support / parallel interface / parallel interface in rfbi mode (mipi dbi protocol) / transaction timing diagrams section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 6-40. dss timing requirements rfbi mode mipi dbi 2.0 - lcd panel no. parameter opp100 opp50 unit min max min max dr0 t su(dv-rdh) setup time, input data rfbi_da[15:0] valid to output 7.3 6.3 ns read enable rfbi_rd high dr1 t h(rdh-div) hold time, output read enable rfbi_rd high to input data 10.6 9.6 ns rfbi_da[15:0] invalid t d(data sampled) input data rfbi_da[15:0] sampled at the end of the n (1) n (1) ns access time (1) n = (accesstime) * (timeparagranularity + 1) * l4clk table 6-41. dss switching characteristics rfbi mode mipi dbi 2.0 - lcd panel parameter opp100 opp50 unit min max min max t w(wrh) pulse duration, output write enable rfbi_wr high a (1) a (1) ns t w(wrl) pulse duration, output write enable rfbi_wr low b (2) b (2) ns t d(a0-wrl) delay time, output command/data control rfbi_a0 transition to c (3) c (3) ns output write enable rfbi_wr low t d(wrh-a0) delay time, output write enable rfbi_wr high to output d (4) d (4) ns command/data control rfbi_a0 transition t d(csx-wrl) delay time, output chip select rfbi_csx (14) low to output write e (5) e (5) ns enable rfbi_wr low t d(wrh-csxh) delay time, output write enable rfbi_wr high to output chip select f (6) f (6) ns rfbi_csx (14) high t d(dv) output data rfbi_da[15:0] valid g (7) g (7) ns t d(a0h-rdl) delay time, output command/data control rfbi_a0 high to output h (8) h (8) ns read enable rfbi_rd low t d(rdlh-a0) delay time, output read enable rfbi_rd high to output i (9) i (9) ns command/data control rfbi_a0 transition t w(rdh) pulse duration, output read enable rfbi_rd high j (10) j (10) ns t w(rdl) pulse duration, output read enable rfbi_rd low k (11) k (11) ns t d(rdl-csxl) delay time, output read enable rfbi_rd low to output chip select l (12) l (12) ns rfbi_csx (14) low t d(rdh-csxh) delay time, output read enable rfbi_rd high to output chip select m (13) m (13) ns rfbi_csx (14) high t r(wr) rise time, output write enable rfbi_wr 10 10 ns t f(wr) fall time, output write enable rfbi_wr 10 10 ns t r(a0) rise time, output command/data control rfbi_a0 10 10 ns t f(a0) fall time, output command/data control rfbi_a0 10 10 ns t r(csx) rise time, output chip select rfbi_csx (14) 10 10 ns 206 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-41. dss switching characteristics rfbi mode mipi dbi 2.0 - lcd panel (continued) parameter opp100 opp50 unit min max min max t f(csx) fall time, output chip select rfbi_csx (14) 10 10 ns t r(d) rise time, output data rfbi_da[15:0] 10 10 ns t f(d) fall time, output data rfbi_da[15:0] 10 10 ns t r(rd) rise time, output read enable rfbi_rd 10 10 ns t f(rd) fall time, output read enable rfbi_rd 10 10 ns (1) a = (wecycletime C weofftime) * (timeparagranularity + 1) * l4clk (2) b = (weofftime C weontime) * (timeparagranularity + 1) * l4clk (3) c = weontime * (timeparagranularity + 1) * l4clk (4) d = (wecycletime + cspulsewidth C weofftime) * (timeparagranularity + 1) * l4clk if mode write to read or read to write is enabled (5) e = (weontime C csontime) * (timeparagranularity + 1) * l4clk (6) f = (csofftime C weofftime) * (timeparagranularity + 1) * l4clk (7) g = wecycletime * (timeparagranularity + 1) * l4clk (8) h = reontime * (timeparagranularity + 1) * l4clk (9) i = (recycletime + cspulsewidth C reofftime) * (timeparagranularity + 1) * l4clk if mode write to read or read to write is enabled (10) j = (recycletime C reofftime) * (timeparagranularity + 1) * l4clk (11) k = (reofftime C reontime) * (timeparagranularity + 1) * l4clk (12) l = (reontime C csontime) * (timeparagranularity + 1) * l4clk (13) m = (csofftime C reofftime) * (timeparagranularity + 1) * l4clk (14) in rfbi_csx, x is equal to 0 or 1. (1) in rfbi_csx, x is equal to 0 or 1. (2) rfbi_data[n:0], n up to 15 (3) for more information, see the dss chapter in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). figure 6-32. dss rfbi mode mipi dbi 2.0 lcd panel command / data write copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 207 submit documentation feedback product folder link(s): dm3730 dm3725 rfbi_a0 rfbi_csx rfbi_wr rfbi_da[n:0] rfbi_rd rfbi_te_vsync[1:0] rfbi_hsync[1:0] data0 data1 csontime csofftime weontime weofftime csontime csofftime weontime weofftime cspulsewidth wecycletime wecycletime swps038-057
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in rfbi_csx, x is equal to 0 or 1. (2) rfbi_data[n:0], n up to 15 (3) for more information, see the dss chapter in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). figure 6-33. dss rfbi mode mipi dbi 2.0 lcd panel command / data read (1) in rfbi_csx, x is equal to 0 or 1. (2) rfbi_data[n:0], n up to 15 (3) for more information, see the dss chapter in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). figure 6-34. dss rfbi mode mipi dbi 2.0 lcd panel command / data write to read and read to write modes 208 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 rfbi_a0 rfbi_csx rfbi_rd rfbi_da[n:0] rfbi_wr rfbi_te_vsync[1:0] rfbi_hsync[1:0] data0 data1 csontime reofftime cspulsewidth accesstime csontime csofftime reontime reofftime accesstime recycletime dr1 swps038-058 recycletime csofftime reontime dr0 rfbi_a0 rfbi_csx rfbi_wr rfbi_rd rfbi_da[n:0] rfbi_te_vsync[1:0] rfbi_hsync[1:0] write read write csontime csofftime weofftime wecycletime cspulsewidth recycletime accesstime csontime csofftime reofftime cspulsewidth csontime weofftime csofftime wecycletime swps038-059 weontime reontime weontime
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 6.5.2.2.2 dss parallel interface rfbi mode pico dlp the remote frame buffer interface (rfbi) module can provide also the necessary control signals and data to interface to the pico dlp driver of the pico dlp panel. table 6-42 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-35 ). table 6-42. dss timing conditions rfbi mode pico dlp timing condition parameter value unit min max output condition c load output load capacitance (1) 5 pf (1) buffer strength configuration: lb0 = 0 to use pico dlp application, rfbi register must be configured as shown in table 6-43 : table 6-43. dss register configuration rfbi mode pico dlp description register and bit field (1) bit values selection parallel mode rfbi_configi and [1:0] 0b11: 16-bit parallel output interface parallelmode selected time granularity (multiplies signal timing rfbi_configi [4] 0b0: x2 latency disable latencies by 2). andtimegranularity cs signal assertion time from start access rfbi_onoff_timei and [3:0] 0b0000 time csontime cs signal de-assertion time from start access rfbi_onoff_timei and [9:4] 0b000100: 4 cycles time csofftime we signal assertion time from start access rfbi_onoff_timei and [13:10] 0b0000 time weontime we signal de-assertion time from start access rfbi_onoff_timei and [19:14] 0b000010: 2 cycles time weofftime re signal assertion time from start access rfbi_onoff_timei and [23:20] 0b0000 time reontime re signal de-assertion time from start access rfbi_onoff_timei and [29:24] 0b000000 time reofftime write cycle time rfbi_cycle_timei and [5:0] 0b000100: 4 cycles wecycletime read cycle time rfbi_cycle_timei and [11:6] 0b000000 recycletime cs pulse width rfbi_cycle_timei and [17:12] 0b000000 cspulsewidth read to write cs pulse width enable rfbi_cycle_timei and [18] 0b0 rwenable read to read cs pulse width enable rfbi_cycle_timei and [19] 0b0 rrenable write to write cs pulse width enable rfbi_cycle_timei and [20] 0b0 wwenable write to read cs pulse width enable rfbi_cycle_timei and [21] 0b0 wrenable from start access time to clk rising edge rfbi_cycle_timei and [27:22] 0b000000 used for the first data capture accesstime (1) i is equal to 0 or 1. for more information, see the dss chapter in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 209 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-44. dss switching characteristics rfbi mode pico dlp (15) (17) (18) parameter opp100 opp50 unit min max min max t w(wrh) pulse duration, output write enable rfbi_wr high a (1) a (1) ns t w(wrl) pulse duration, output write enable rfbi_wr low b (2) b (2) ns t d(a0-wrl) delay time, output command/data control rfbi_a0 c (3) c (3) ns transition to output write enable rfbi_wr low t d(wrh-a0) delay time, output write enable rfbi_wr high to output d (4) d (4) ns command/data control rfbi_a0 transition t d(csx-wrl) delay time, output chip select rfbi_csx (14) low to output e (5) e (5) ns write enable rfbi_wr low t d(wrh-csxh) delay time, output write enable rfbi_wr high to output f (6) f (6) ns chip select rfbi_csx (14) high t d(datav) output data rfbi_da[15:0] (16) valid g (7) g (7) ns t d(skew) skew between output write enable falling rfbi_wr and 15.5 15.5 ns output data rfbi_da[15:0] (16) high or low t d(a0h-rdl) delay time, output command/data control rfbi_a0 high to h (8) h (8) ns output read enable rfbi_rd low t d(rdlh-a0) delay time, output read enable rfbi_rd high to output i (9) i (9) ns command/data control rfbi_a0 transition t w(rdh) pulse duration, output read enable rfbi_rd high j (10) j (10) ns t w(rdl) pulse duration, output read enable rfbi_rd low k (11) k (11) ns t d(rdl-csxl) delay time, output read enable rfbi_rd low to output chip l (12) l (12) ns select rfbi_csx (14) low t d(rdl-csxh) delay time, output read enable rfbi_rd low to output chip m (13) m (13) ns select rfbi_csx (14) high t r(wr) rise time, output write enable rfbi_wr 7 7 ns t f(wr) fall time, output write enable rfbi_wr 7 7 ns t r(a0) rise time, output command/data control rfbi_a0 7 7 ns t f(a0) fall time, output command/data control rfbi_a0 7 7 ns t r(csx) rise time, output chip select rfbi_csx (14) 7 7 ns t f(csx) fall time, output chip select rfbi_csx (14) 7 7 ns t r(d) rise time, output data rfbi_da[15:0] (16) 7 7 ns t f(d) fall time, output data rfbi_da[15:0] (16) 7 7 ns t r(rd) rise time, output read enable rfbi_rd 7 7 ns t f(rd) fall time, output read enable rfbi_rd 7 7 ns csontime cs signal assertion time from start access time - 0 (19) ns rfbi_onoff_timei register csofftime cs signal de-assertion time from start access time - 40 (19) ns rfbi_onoff_timei register weontime we signal assertion time from start access time - 0 (19) ns rfbi_onoff_timei register weofftime we signal de-assertion time from start access time - 20 (19) ns rfbi_onoff_timei register reontime re signal assertion time from start access time - - ns rfbi_onoff_timei register reofftime re signal de-assertion time from start access time - - ns rfbi_onoff_timei register wecycletime write cycle time - rfbi_cycle_timei register 40 (19) ns recycletime read cycle time - rfbi_cycle_timei register - ns cspulsewidth cs pulse width - rfbi_cycle_timei register 0 (19) ns 210 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) a = (wecycletime C weofftime) * (timeparagranularity + 1) * l4clk (2) b = (weofftime C weontime) * (timeparagranularity + 1) * l4clk (3) c = weontime * (timeparagranularity + 1) * l4clk (4) d = (wecycletime + cspulsewidth C weofftime) * (timeparagranularity + 1) * l4clk if mode write to read or read to write is enabled. (5) e = (weontime C csontime) * (timeparagranularity + 1) * l4clk (6) f = (csofftime C weofftime) * (timeparagranularity + 1) * l4clk (7) g = wecycletime * (timeparagranularity + 1) * l4clk (8) h = reontime * (timeparagranularity + 1) * l4clk (9) i = (recycletime + cspulsewidth C reofftime) * (timeparagranularity + 1) * l4clk if mode write to read or read to write is enabled. (10) j = (recycletime C reofftime) * (timeparagranularity + 1) * l4clk (11) k = (reofftime C reontime) * (timeparagranularity + 1) * l4clk (12) l = (reontime C csontime) * (timeparagranularity + 1) * l4clk (13) m = (csofftime C reofftime) * (timeparagranularity + 1) * l4clk (14) in rfbi_csx, x is equal to 0 or 1. (15) see section 4.3.4 , processor clocks . (16) 16-bit parallel output interface is selected in dss register. (17) at opp100, l4 clock is 100 mhz and at opp50, l4 clock is 50 mhz. (18) rfbi_wr must be at 25 mhz. (19) these values are calculated by the following formula: rfbi register (value) * l4 clock (ns). figure 6-35. dss rfbi mode pico dlp command / data write (1) (2) (1) in rfbi_csx, x is equal to 0 or 1. (2) rfbi_da[n:0], n up to 15 copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 211 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-118 rfbi_hsync[1:0] rfbi_a0 rfbi_csx rfbi_wr rfbi_da[n:0] rfbi_rd rfbi_te_vsync[1:0] data0 data1 csontime csofftime weofftime csontime csofftime weontime weofftime cspulsewidth wecycletime weontime wecycletime
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.6 serial communications interfaces 6.6.1 multichannel buffered serial port (mcbsp) note for more information, see multi-channel buffered serial port chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the multichannel buffered serial port (mcbsp) provides a full duplex direct serial interface between the chip and other devices in a system such as other application chips, codecs. it can accommodate a wide range of peripherals and clocked frame oriented protocols (i2s, pcm, t ) due to its high level of versatility. mcbsp may support two types of data transfer at the system level: ? the full cycle mode, for which one clock period is used to transfer the data, generated on one edge and captured on the same edge (one clock period later). ? the half cycle mode, for which one half clock period is used to transfer the data, generated on one edge and captured on the opposite edge (one half clock period later). note that a new data is generated only every clock period, which secures the required hold time. the interface clock (clkx/clkr) activation edge (data/frame sync capture and generation) has to be configured accordingly with the external peripheral (activation edge capability) and the type of data transfer required at the system level. depending on the number of pins, mcbsp supports either: ? 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins ? 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. the clkx and fsx pins are internally looped back, via software configuration, respectively to the clkr and fsr internal signals for data receive. mcbsp1 supports the 6-pin mode. mcbsp2, 3, 4, and 5 support only the 4-pin mode. the following sections describe the timing characteristics for applications in normal mode (that is, mcbspx connected to one peripheral) and t applications in multipoint mode. 6.6.1.1 mcbsp timing conditions normal mode table 6-46 through table 6-70 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-36 through figure 6-43 ). table 6-45. mcbsp timing conditions normal mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output condition c load output load capacitance (1) 10 pf (1) buffer strength configuration: C mcbsp4 - set #1: lb0 = 1. C otherwise: lb0 = 0. 212 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-46. mcbsp output clock characteristics normal mode (4) parameter opp100 opp50 unit min max min max mcbsp1 tc(clk) cycle time, mcbsp1_clkx (multiplexing mode 0) / 48 24 mhz mcbsp1_clkr (multiplexing mode 0 & 2) mcbsp2 tc(clk) cycle time, mcbsp2_clkx (multiplexing mode 0) 48 24 mhz mcbsp3 tc(clk) cycle time, mcbsp3_clkx io set 1 32 16 mhz (multiplexing mode 0) io set 2 48 24 (multiplexing mode 1) io set 3 48 24 (multiplexing mode 2) mcbsp4 tc(clk) cycle time, mcbsp4_clkx io set 1 48 16 mhz (multiplexing mode 0) io set 3 32 16 (multiplexing mode 2) mcbsp5 tc(clk) cycle time, mcbsp5_clkx io set 2 32 16 mhz (multiplexing mode 1) t w(clkh) typical pulse duration, mcbsp1_clkr / mcbspx_clkx high (2) 0.5*p (1) 0.5*p (1) ns t w(clkl) typical pulse duration, mcbsp1_clkr / mcbspx_clkx low (2) 0.5*p (1) 0.5*p (1) ns t dc(clk) duty cycle error, mcbsp1_clkr / mcbspx_clkx (2) C 0.75 0.75 C 0.75 0.75 ns jitter, mcbsp1_clkr / mcbspx_clkx (3) / mcbsp_clks -0.40 0.40 -0.40 0.40 ns (1) p = mcbspy_clkx (2) or mcbsp1_clkr output clock period in ns (2) in mcbspy, y is equal to 1, 2, 3, 4, or 5. (3) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. (4) see section 4.3.4 , processor clocks . 6.6.1.1.1 rising edge as activation mode 6.6.1.1.1.1 timing with rising edge as activation edge receive mode table 6-47. mcbsp1, 2, and 3 (sets #2 and #3) timing requirements rising edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b3 t su(drv-clkae) setup time, mcbspx_dr valid before master 4.36 8.63 ns mcbsp1_clkr / mcbspx_clkx active edge slave 3.67 7.94 ns b4 t h(clkae-drv) hold time, mcbspx_dr valid after master 1.01 1.01 ns mcbsp1_clkr / mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsv-clkae) setup time, mcbsp1_fsr / mcbspx_fsx valid before 3.67 7.94 ns mcbsp1_clkr / mcbspx_clkx active edge b6 t h(clkae-fsv) hold time, mcbsp1_fsr / mcbspx_fsx valid after 0.5 0.5 ns mcbsp1_clkr / mcbspx_clkx active edge copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 213 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). (2) see section 4.3.4 , processor clocks . table 6-48. mcbsp1, 2, and 3 (sets #2 and #3) switching characteristics rising edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkae-fsv) delay time, mcbsp1_clkr / mcbspx_clkx active edge to 0.7 14.79 0.7 29.58 ns mcbsp1_fsr / mcbspx_fsx valid (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). (2) see section 4.3.4 , processor clocks . table 6-49. mcbsp4 (set #1) timing requirements rising edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b3 t su(drv-clkxae) setup time, mcbspx_dr valid before master 2.87 8.63 ns mcbspx_clkx active edge slave 3.67 7.94 ns b4 t h(clkxae-drv) hold time, mcbspx_dr valid after master 1.01 1.01 ns mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.67 7.94 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-51 and table 6-52 . (2) see section 4.3.4 , processor clocks . table 6-50. mcbsp4 (set #1) switching characteristics rising edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 16.56 0.7 33.12 ns valid (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-51 and table 6-52 . (2) see section 4.3.4 , processor clocks . table 6-51. mcbsp3 (set #1), 4 (set #2), and 5 timing requirements rising edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b3 t su(drv-clkxae) setup time, mcbspx_dr valid before master 6.49 12.90 ns mcbspx_clkx active edge slave 5.80 12.21 ns b4 t h(clkxae-drv) hold time, mcbspx_dr valid after master 1.01 1.01 ns mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 5.81 12.21 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge 214 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-47 and table 6-48 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). (2) see section 4.3.4 , processor clocks . table 6-52. mcbsp3 (set #1), 4 (set #2), and 5 switching characteristics rising edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.18 0.7 44.37 ns valid (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-47 and table 6-48 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins) (2) see section 4.3.4 , processor clocks . (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. figure 6-36. mcbsp rising edge receive timing in master mode (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. figure 6-37. mcbsp rising edge receive timing in slave mode 6.6.1.1.1.2 timing with rising edge as activation edge transmit mode table 6-53. mcbsp1, 2, and 3 (sets #2 and #3) timing requirements rising edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.67 7.94 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 215 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-062 mcbspx_clkr mcbspx_fsr mcbspx_dr d7 d6 d5 b2 b2 b3 b4 swps038-063 mcbspx_clkr mcbspx_fsr mcbspx_dr d7 d6 d5 b3 b4 b5 b6
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). (2) see section 4.3.4 , processor clocks . table 6-54. mcbsp1, 2, and 3 (sets #2 and #3) switching characteristics rising edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 14.79 0.7 29.58 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 14.79 0.6 29.58 ns mcbspx_dx valid slave 0.6 13.89 0.6 28.68 ns (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). (2) see section 4.3.4 , processor clocks . table 6-55. mcbsp4 (set #1) timing requirements rising edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.67 7.94 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-57 and table 6-58 . (2) see section 4.3.4 , processor clocks . table 6-56. mcbsp4 (set #1) switching characteristics rising edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 16.56 0.7 33.12 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 16.56 0.6 33.12 ns mcbspx_dx valid slave 0.6 17.15 0.6 32.22 ns (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-57 and table 6-58 . (2) see section 4.3.4 , processor clocks . table 6-57. mcbsp3 (set #1), 4 (set #2), and 5 timing requirements rising edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 5.81 12.21 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-53 and table 6-54 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). (2) see section 4.3.4 , processor clocks . 216 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-58. mcbsp3 (set #1), 4 (set #2), and 5 switching characteristics rising edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.18 0.7 44.37 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 21.28 0.6 43.47 ns mcbspx_dx valid slave 0.6 21.28 0.6 43.47 ns (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-53 and table 6-54 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). (2) see section 4.3.4 , processor clocks . (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. figure 6-38. mcbsp rising edge transmit timing in master mode (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. figure 6-39. mcbsp rising edge transmit timing in slave mode 6.6.1.1.2 falling edge as activation edge 6.6.1.1.2.1 timing with falling edge as activation edge mode receive mode table 6-59. mcbsp1, 2, 3 (sets #2 and #3) timing requirements falling edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b3 t su(drv-clkae) setup time, mcbspx_dr valid before master 4.36 8.63 ns mcbsp1_clkr / mcbspx_clkx active edge slave 3.67 7.94 ns b4 t h(clkae-drv) hold time, mcbspx_dr valid after master 1.01 1.01 ns mcbsp1_clkr / mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsv-clkae) setup time, mcbsp1_fsr / mcbspx_fsx valid before 3.7 7.94 ns mcbsp1_clkr / mcbspx_clkx active edge b6 t h(clkae-fsv) hold time, mcbsp1_fsr / mcbspx_fsx valid after 0.5 0.5 ns mcbsp1_clkr / mcbspx_clkx active edge copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 217 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-064 mcbspx_clkx mcbspx_fsx mcbspx_dx d7 d6 d5 b2 b2 b8 swps038-065 mcbspx_clkx mcbspx_fsx mcbspx_dx d7 d6 d5 b8 b5 b6
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). (2) see section 4.3.4 , processor clocks . table 6-60. mcbsp1, 2, and 3 (sets #2 and #3) switching characteristics falling edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkae-fsv) delay time, mcbsp1_clkr / mcbspx_clkx active edge to 0.7 14.79 0.7 29.58 ns mcbsp1_fsr / mcbspx_fsx valid (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). (2) see section 4.3.4 , processor clocks . table 6-61. mcbsp4 (set #1) timing requirements falling edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b3 t su(drv-clkxae) setup time, mcbspx_dr valid before master 2.87 8.63 ns mcbspx_clkx active edge slave 3.67 7.94 ns b4 t h(clkxae-drv) hold time, mcbspx_dr valid after master 1.01 1.01 ns mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.67 7.94 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-63 and table 6-64 . (2) see section 4.3.4 , processor clocks . table 6-62. mcbsp4 (set #1) switching characteristics falling edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 16.56 0.7 33.12 ns valid (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-63 and table 6-64 . (2) see section 4.3.4 , processor clocks . table 6-63. mcbsp3 (set #1), 4 (set #2), and 5 timing requirements falling edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b3 t su(drv-clkxae) setup time, mcbspx_dr valid before master 6.5 12.9 ns mcbspx_clkx active edge slave 5.81 12.21 ns b4 t h(clkxae-drv) hold time, mcbspx_dr valid after master 1.01 1.01 ns mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 5.81 12.21 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge 218 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-59 and table 6-60 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). (2) see section 4.3.4 , processor clocks . table 6-64. mcbsp3 (set #1), 4 (set #2), and 5 switching characteristics falling edge and receive mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.19 0.7 44.37 ns valid (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-59 and table 6-60 . (2) see section 4.3.4 , processor clocks . (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. figure 6-40. mcbsp falling edge receive timing in master mode (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. figure 6-41. mcbsp falling edge receive timing in slave mode 6.6.1.1.2.2 timing with falling edge as activation edge transmit mode table 6-65. mcbsp1, 2, and 3 (sets #2 and #3) timing requirements falling edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.67 7.94 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 219 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-067 mcbspx_clkr mcbspx_fsr mcbspx_dr d7 d6 d5 b3 b4 b5 b6 swps038-066 mcbspx_clkr mcbspx_fsr mcbspx_dr d7 d6 d5 b2 b2 b3 b4
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). (2) see section 4.3.4 , processor clocks . table 6-66. mcbsp1, 2, and 3 (sets #2 and #3) switching characteristics falling edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 14.79 0.7 29.58 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 14.79 0.6 29.58 ns mcbspx_dx valid slave 0.6 13.89 0.6 28.68 ns (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). (2) see section 4.3.4 , processor clocks . table 6-67. mcbsp4 (set #1) timing requirements falling edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.67 7.94 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-69 and table 6-70 . (2) see section 4.3.4 , processor clocks . table 6-68. mcbsp4 (set #1) switching characteristics falling edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 16.56 0.7 33.12 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 16.56 0.6 33.12 ns mcbspx_dx valid slave 0.6 17.15 0.6 32.22 ns (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-69 and table 6-70 . (2) see section 4.3.4 , processor clocks . table 6-69. mcbsp3 (set #1), 4 (set #2), and 5 timing requirements falling edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 5.81 12.21 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-66 and table 6-67 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). (2) see section 4.3.4 , processor clocks . 220 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-70. mcbsp3 (set #1), 4 (set #2), and 5 switching characteristics falling edge and transmit mode (1) (2) no. parameter opp100 opp50 unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.18 0.7 44.37 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 21.28 0.6 43.47 ns mcbspx_dx valid slave 0.6 21.28 0.6 43.47 ns (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-66 and table 6-67 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). (2) see section 4.3.4 , processor clocks . (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. figure 6-42. mcbsp falling edge transmit timing in master mode (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. figure 6-43. mcbsp falling edge transmit timing in slave mode 6.6.1.2 mcbsp in tdm multipoint mode (mcbsp3) for t application in multipoint mode, the processor is considered as a slave. table 6-72 and table 6-73 assume testing over the operating conditions and electrical characteristic conditions described below. table 6-71. mcbsp3 (set #3) timing conditions t multipoint mode (1) timing condition parameter value unit min max input conditions t r input signal rise time 1.0 8.5 ns t f input signal fall time 1.0 8.5 ns output condition c load output load capacitance (2) 40 pf (1) for mcbsp3, these timings concern only set #3 (multiplexing mode in mcbsp1 pins) (2) the load setting of the io buffer: lb0 = 0. table 6-72. mcbsp3 (set #3) timing requirements t multipoint mode (4) no. parameter opp100 opp50 unit min max min max 1 / t c(clkxh) frequency, input clock mcbsp3_clkx 6 6 mhz copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 221 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-068 mcbspx_clkx mcbspx_fsx mcbspx_dx d7 d6 d5 b2 b2 b8 swps038-069 mcbspx_clkx mcbspx_fsx mcbspx_dx d7 d6 d5 b8 b5 b6
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-72. mcbsp3 (set #3) timing requirements t multipoint mode (4) (continued) no. parameter opp100 opp50 unit min max min max t w(clkxh) pulse duration, input clock mcbsp3_clkx high 0.5p (1) 0.5p (1) ns t w(clkxl) pulse duration, input clock mcbsp3_clkx low 0.5p (1) 0.5p (1) ns t dc(clkx) duty cycle error, input clock mcbsp3_clkx C 8.14 8.14 C 8.14 8.14 ns b3 (3) t su(drv-clkxae) setup time, input data mcbsp3_dr valid before input 9 9 ns clock mcbsp3_clkx active edge b4 (3) t h(clkxae-drv) hold time, input data mcbsp3_dr valid after input clock 2.4 2.4 ns mcbsp3_clkx active edge b5 (3) t su(fsxv-clkxae) setup time, input frame synchronization mcbsp3_fsx 9 9 ns valid before input clock mcbsp3_clkx active edge b6 (3) t h(clkxae-fsxv) hold time, input frame synchronization mcbsp3_fsx 2.4 2.4 ns valid after input clock mcbsp3_clkx active edge (1) p = input clock mcbsp3_clkx period in ns (2) for mcbsp3, these timings concern only set #3 (multiplexing mode in mcbsp1 pins). (3) see section 6.6.1.1 for corresponding figures. (4) see section 4.3.4 , processor clocks . table 6-73. mcbsp3 (set #3) switching characteristics t multipoint mode (1) no. parameter opp100 opp50 unit min max min max b8 (2) t d(clkxae-dxv) delay time, mcbsp3_clkx active edge to output data 0.6 15.89 0.6 28.68 ns mcbsp3_dx valid (1) for mcbsp3, these timings concern only set #3 (multiplexing mode in mcbsp1 pins). (2) see section 6.6.1.1 for corresponding figures. 222 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 6.6.2 multichannel serial port interface (mcspi) note for more information, see multichannel spi chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). mcspi allows a duplex, synchronous, serial communication between a local host and spi compliant external devices. the following timings are applicable to the different configurations of mcspi in master/slave mode for any mcspi and any channel (n). 6.6.2.1 mcspi slave mode in slave mode, mcspi initiates data transfer on the data lines (mcspix_somi, mcspix_simo) when it receives an spi clock (mcspix_clk) from the external spi master device. table 6-75 and table 6-76 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-44 and figure 6-45 ). table 6-74. mcspi timing conditions slave mode timing condition parameter value unit input conditions t r input signal rise time 4 ns t f input signal fall time 4 ns output condition c load output load capacitance (1) 20 pf (1) the load setting of the io buffer: lb0 = 1. table 6-75. mcspi timing requirements slave mode (1) (3) no. parameter opp100 opp50 unit min max min max ss0 1/t c(clk) frequency, mcspix_clk 24 12 mhz ss1 t w(clk) pulse duration, mcspix_clk high or low 0.45*p (2) 0.55*p (2) 0.45*p (2) 0.55*p (2) ns ss2 t su(simov-clkae) setup time, mcspix_simo valid before mcspix_clk 4.2 9.5 ns active edge ss3 t h(simov-clkae) hold time, mcspix_simo valid after mcspix_clk active 4.6 9.9 ns edge ss4 t su(cs0v-clkfe) setup time, mcspix_cs0 valid before mcspix_clk first 13.8 28.6 ns edge ss5 t h(cs0i-clkle) hold time, mcspix_cs0 invalid after mcspix_clk last 13.8 28.6 ns edge (1) in mcspix, x is equal to 1, 2, 3, or 4. (2) p = mcspix_clk clock period (3) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 223 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-76. mcspi switching characteristics slave mode (1) (3) (4) no. parameter opp100 opp50 unit min max min max ss6 t d(clkae-somiv) delay time, mcspix_clk active edge to mcspix_somi 1.8 15.9 3.2 31.7 ns shifted ss7 t d(cs0ae-somiv) delay time, mcspix_cs0 active edge to modes 0 15.9 31.7 ns mcspix_somi shifted and 2 (2) (1) in mcspix, x is equal to 1, 2, 3, or 4. (2) the polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable: C mcspix_clk (1) phase programmable with the bit pha of mcspi_ch(i)conf register: pha = 0 (modes 0 and 2) for more information, see the mcspi environment chapter, data format configurations section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) for modes and phase correspondence description. (3) this timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and capture input data. (4) see section 4.3.4 , processor clocks . (1) the active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is software configurable with the bit mcspi_ch(i)conf[1] = pol and the bit mcspi_ch(i)conf[0] = pha. (2) the polarity of mcspi_cs is software configurable with the bit mcspi_ch(i)conf[6] = epol. figure 6-44. mcspi slave mode transmit 224 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 mcspi_cs(in) mcspi_clk(in)mcspi_clk(in) mcspi_somi(out) mcspi_cs(in) mcspi_clk(in)mcspi_clk(in) mcspi_somi(out) bit nC1 bit nC2 bit nC3 bit nC4 bit 0 bit nC1 bit nC2 bit nC3 bit 1 bit 0 pha=0epol=1 pol=0 pol=1 pol=0 pol=1 pha=1epol=1 ss6 ss1 ss0 ss1 ss0 ss1 ss0 ss1 ss0 ss6 ss6 ss4 ss5 ss7 ss4 ss1 ss1 ss1 ss1 ss6 ss6 ss6 ss5 swps038-070
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) the active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is software configurable with the bit mcspi_ch(i)conf[1] = pol and the bit mcspi_ch(i)conf[0] = pha. (2) the polarity of mcspi_cs is software configuable with the bit mcspi_ch(i)conf[6] = epol. figure 6-45. mcspi slave mode receive copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 225 submit documentation feedback product folder link(s): dm3730 dm3725 mcspi_cs(in) mcspi_clk(in)mcspi_clk(in) mcspi_simo(in) mcspi_cs(in) mcspi_clk(in)mcspi_clk(in) mcspi_simo(in) bit nC1 bit nC2 bit nC3 bit nC4 bit 0 bit nC1 bit nC2 bit nC3 bit 1 bit 0 pha=0epol=1 pol=0 pol=1 pol=0 pol=1 pha=1epol=1 ss1 ss1 ss1 ss1 ss4 ss5 ss4 ss5 ss1 ss1 ss1 ss1 ss2 ss3 ss3 ss2 ss2 ss3 ss2 ss3 swps038-071 ss0 ss0 ss0 ss0
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.6.2.2 mcspi master mode in master mode, mcspi supports multichannel communication. mcspi initiates a data transfer on the data lines (spidat [1:0]) and generates clock (spiclk) and control signals (spien) to a single spi slave device at a time. table 6-78 and table 6-81 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-46 and figure 6-47 ). table 6-77. mcspi timing conditions master mode (1) timing condition parameter value unit min max input conditions t r input signal rise time 4 ns t f input signal fall time 4 ns output conditions mcspi1, mcspi2, mcspi3, and mcspi4 c load output load capacitance for spix_csn signals 20 pf mcspi2 and mcspi3 c load output load capacitance for spix_clk and spix_simo 30 pf mcspi1 and mcspi4 c load output load capacitance for spix_clk and spix_simo 20 pf (1) buffer strength configuration: lb0 = 1. table 6-78. mcspi1, 2, and 4 timing requirements master mode (1) (2) no. parameter opp100 opp50 unit min max min max sm2 t su(somiv-clkae) setup time, mcspix_somi valid before mcspix_clk 1.1 1.5 ns active edge sm3 t h(somiv-clkae) hold time, mcspix_somi valid after mcspix_clk active 1.9 2.8 ns edge (1) in mcspix, x is equal to 1, 2, or 4. in mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4. (2) see section 4.3.4 , processor clocks . table 6-79. mcspi1, 2, and 4 switching characteristics master mode (1) (6) no. parameter opp100 opp50 unit min max min max sm0 1/t c(clk) frequency, mcspix_clk 48 24 mhz sm1 t w(clk) pulse duration, mcspix_clk high or low 0.45*p (3) 0.55*p (3) 0.45*p (3) 0.55*p (3) ns t r(clk) rise time, output clock mcspi1_clk and mcspi4_clk 5.72 5.68 ns rise time, output clock mcspi2_clk 7.33 7.31 t f(clk) fall time, output clock mcspi1_clk and mcspi4_clk 5.22 5.21 ns fall time, output clock mcspi2_clk 6.77 6.71 sm4 t d(clkae-simov) delay time, mcspix_clk active edge to mcspix_simo C 2.1 5.0 C 2.1 11.3 ns shifted sm5 t d(csna-clkfe) delay time, mcspix_csi active to modes 1 and 3 (2) a (4) C 3.2 a (4) C 4.4 ns mcspix_clk first edge modes 0 and 2 (2) b (5) C 3.2 b (5) C 4.4 ns sm6 t d(clkle-csni) delay time, mcspix_clk last modes 1 and 3 (2) b (5) C 3.2 b (5) C 4.4 ns edge to mcspix_csi inactive modes 0 and 2 (2) a (4) C 3.2 a (4) C 4.4 ns sm7 t d(csnae-simov) delay time, mcspix_csi active edge to mcspix_simo 5.0 11.3 ns shifted 226 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in mcspix, x is equal to 1, 2, or 4. in mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4. (2) the polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable: C mcspix_clk (1) phase programmable with the bit pha of mcspi_ch(i)conf register: pha = 1 (modes 1 and 3). C mcspix_clk (1) phase programmable with the bit pha of mcspi_ch(i)conf register: pha = 0 (modes 0 and 2). for more information, see the mcspi environment chapter, data format configurations section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) for modes and phase correspondence description. (3) p = mcspix_clk clock period (4) case p = 20.8 ns, a = (tcs+0.5)*p (3) (tcs is a bit field of mspi_chconfx[26:25] register). case p > 20.8 ns, a = tcs*p (3) (tcs is a bitfield of mspi_chconfx[26:25] register). for more information, see the mcspi chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (5) b = tcs*p (3) (tcs is a bit field of mspi_chconfx[26:25] register). for more information, see the mcspi chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) see section 4.3.4 , processor clocks . table 6-80. mcspi3 timing requirements master mode (1) no. parameter opp100 opp50 unit min max min max sm2 t su(somiv-clkae) setup time, mcspi3_somi valid before mcspi3_clk 1.5 4.3 ns active edge sm3 t h(somiv-clkae) hold time, mcspi3_somi valid after mcspi3_clk active 2.8 5.9 ns edge (1) see section 4.3.4 , processor clocks . table 6-81. mcspi3 switching characteristics master mode (1) (2) (6) no. parameter opp100 opp50 unit min max min max sm0 1/t c(clk) frequency, mcspi3_clk 24 12 mhz sm1 t w(clkh) pulse duration, mcspi3_clk high or low 0.45*p (3) 0.55*p (3) 0.45*p (3) 0.55*p (3) ns t r(clk) rise time, output clock mcspi3_clk cbp 7.33 7.31 ns balls: ae2 / ae13 cbp 4.31 4.30 ball: h26 t f(clk) fall time, output clock mcspi3_clk cbp 6.77 6.71 ns balls: ae2 / ae13 cbp 4.0 4.0 ball: h26 sm4 t d(clk-simo) delay time, mcspi3_clk active edge to mcspi3_simo C 2.1 11.3 C 5.3 23.6 ns shifted sm5 t d(csn-clk) delay time, mcspi3_csi active to modes 1 a (4) C 4.4 a (4) C ns mcspi3_clk first edge and 3 10.1 modes 0 b (5) C 4.4 b (5) C ns and 2 10.1 sm6 t d(clk-csn) delay time, mcspi3_clk last edge to modes 1 b (5) C 4.4 b (5) C ns mcspi3_csi inactive and 3 10.1 modes 0 a (4) C 4.4 a (4) C ns and 2 10.1 sm7 t d(csn-simo) delay time, mcspi3_csi active edge to modes 0 11.3 23.6 ns mcspi3_simo shifted and 2 copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 227 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in mcspi3_csn, n is equal to 0 or 1. the polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched is all software configurable. C mcspi3_clk phase programmable with the bit pha of mcspi_ch(i)conf register: pha = 1 (modes 1 and 3). C mcspi3_clk phase programmable with the bit pha of mcspi_ch(i)conf register: pha = 0 (modes 0 and 2). for more information, see the mcspi environment chapter, data format configurations section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ) for modes and phase correspondence description. (2) this timing applies to all configurations regardless of mcspi3_clk polarity and which clock edges are used to drive output data and capture input data. (3) p = mcspi3_clk clock period (4) case p = 20.8 ns, a = (tcs + 0.5)*p (3) (tcs is a bit field of mspi_chconfx[26:25] register). case p > 20.8 ns, a = tcs*p (3) (tcs is a bit field of mspi_chconfx[26:25] register). for more information, see the mcspi chapter of am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (5) b = tcs*p (3) (tcs is a bit field of mspi_chconfx[26:25] register). for more information, see the mcspi chapter of am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) see section 4.3.4 , processor clocks . (1) the active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is software configurable with the bit mcspi_ch(i)conf[1] = pol and the bit mcspi_ch(i)conf[0] = pha. (2) the polarity of mcspi_ncs is software configuable with the bit mcspi_ch(i)conf[6] = epol. figure 6-46. mcspi master mode transmit 228 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 mcspi_cs(out) mcspi_clk(out)mcspi_clk(out) mcspi_simo(out) mcspi_cs(out) mcspi_clk(out)mcspi_clk(out) mcspi_simo(out) bit nC1 bit nC2 bit nC3 bit nC4 bit 0 bit nC1 bit nC2 bit nC3 bit 1 bit 0 pha=0epol=1 pol=0 pol=1 pha=1 epol=1 pol=0 pol=1 sm5 sm6 sm4 sm1 sm0 sm1 sm0 sm5 sm6 sm1 sm0 sm1 sm0 sm4 sm7 sm4 sm1 sm1 sm1 sm1 sm4 sm4 sm4 swps038-072
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) the active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is software configurable with the bit mcspi_ch(i)conf[1] = pol and the bit mcspi_ch(i)conf[0] = pha. (2) the polarity of mcspi_ncs is software configuable with the bit mcspi_ch(i)conf[6] = epol. figure 6-47. mcspi master mode receive 6.6.3 multiport full-speed universal serial bus (fs-usb) note for more information, see high-speed usb host subsystem and high-speed usb otg controller / high-speed usb host subsystem section of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the processor provides three usb ports working in full- and low-speed data transactions (up to 12mbit/s). when connected to either a serial link controller or a serial phy (phy interface modes) it supports: ? 6-pin (tx: dat/se0 or tx: dp/ ) unidirectional mode ? 4-pin bidirectional mode ? 3-pin bidirectional copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 229 submit documentation feedback product folder link(s): dm3730 dm3725 mcspi_cs(out) mcspi_clk(out)mcspi_clk(out) mcspi_somi(in) mcspi_cs(out) mcspi_clk(out)mcspi_clk(out) mcspi_somi(in) bit nC1 bit nC2 bit nC3 bit n-4 bit 0 bit nC1 bit nC2 bit nC3 bit 1 bit 0 pha=0epol=1 pha=1 epol=1 pol=0 pol=1 pol=0pol=1 sm5 sm6 sm1 sm0 sm1 sm0 sm5 sm6 sm1 sm0 sm1 sm0 sm1 sm1 sm1 sm1 sm3 sm3 sm3 sm3 sm2 sm2 sm2 sm2 swps038-073
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.6.3.1 fs-usb unidirectional standard 6-pin mode table 6-83 and table 6-84 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-48 ). table 6-82. ls- / fs-usb timing conditions unidirectional standard 6-pin mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output condition c load output load capacitance (1) 15 pf (1) buffer strength configuration: lb0 = 1. table 6-83. ls- / fs-usb timing requirements unidirectional standard 6-pin mode (1) (2) no. parameter opp100 opp50 unit min max min max fsu1 t d(vp,vm) time duration, mmx_rxdp and mmx_rx low together 14 14 ns during transition fsu2 t d(vp,vm) time duration, mmx_rxdp and mmx_rx high together 8 8 ns during transition fsu3 t d(rcvu0) time duration, mmx_rrxcv undefine during a single 14 14 ns end 0 (mmx_rxdp and mmx_rx low together) fsu4 t d(rcvu1) time duration, mmx_rxrcv undefine during a single 8 8 ns end 1 (mmx_rxdp and mmx_rx high together) (1) in mmx, x is equal to 0, 1, or 2. (2) see section 4.3.4 , processor clocks . table 6-84. ls- / fs-usb switching characteristics unidirectional standard 6-pin mode (1) (2) no. parameter opp100 opp50 unit min max min max fsu5 t d(txenl-dv) delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns fsu6 t d(txenl-se0v) delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns fsu7 t s(d-se0) skew between mmx_txdat and mmx_txse0 transition 1.5 1.5 ns fsu8 t d(di-txenh) delay time, mmx_txdat invalid to mmx_txen_n high 81.8 81.8 ns fsu9 t d(se0i-txenh) delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 81.8 ns (1) in mmx, x is equal to 0, 1, or 2. (2) see section 4.3.4 , processor clocks . 230 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) in mmx, x is equal to 0, 1, or 2. figure 6-48. ls- / fs-usb unidirectional standard 6-pin mode 6.6.3.2 fs-usb bidirectional standard 4-pin mode table 6-86 and table 6-87 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-49 ). table 6-85. ls- / fs-usb timing conditions bidirectional standard 4-pin mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output condition c load output load capacitance (1) 15 pf (1) buffer strength configuration: lb0 = 1. table 6-86. ls- / fs-usb timing requirements bidirectional standard 4-pin mode (1) (2) no. parameter opp100 opp50 unit min max min max fsu10 t d(d,se0) time duration, mmx_txdat and mmx_txse0 low 14 14 ns together during transition fsu11 t d(d,se0) time duration, mmx_txdat and mmx_txse0 high 8 8 ns together during transition fsu12 t d(rcvu0) time duration, mmx_rrxcv undefine during a single 14 14 ns end 0 (mmx_txdat and mmx_txse0 low together) fsu13 t d(rcvu1) time duration, mmx_rxrcv undefine during a single 8 8 ns end 1 (mmx_txdat and mmx_txse0 high together) (1) in mmx, x is equal to 0, 1, or 2. (2) see section 4.3.4 , processor clocks . table 6-87. ls- / fs-usb switching characteristics bidirectional standard 4-pin mode (1) (2) no. parameter opp100 opp50 unit min max min max fsu14 t d(txenl-dv) delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns fsu15 t d(txenl-se0v) delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns fsu16 t s(d-se0) skew between mmx_txdat and mmx_txse0 transition 1.5 1.5 ns fsu17 t d(dv-txenh) delay time, mmx_txdat invalid before mmx_txen_n 81.8 81.8 ns high copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 231 submit documentation feedback product folder link(s): dm3730 dm3725 mmx_txen_n mmx_txdat mmx_txse0 mmx_rxdp mmx_rxdm mmx_rxrcv fsu5 fsu6 fsu7 fsu1 fsu1 fsu2 fsu2 fsu3 fsu4 fsu8 fsu9 transmit receive swps038-074
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-87. ls- / fs-usb switching characteristics bidirectional standard 4-pin mode (1) (2) (continued) no. parameter opp100 opp50 unit min max min max fsu18 t d(se0v-txenh) delay time, mmx_txse0 invalid before mmx_txen_n 81.8 81.8 ns high (1) in mmx, x is equal to 0, 1, or 2. (2) see section 4.3.4 , processor clocks . (1) in mmx, x is equal to 0, 1, or 2. figure 6-49. ls- / fs-usb bidirectional standard 4-pin mode 6.6.3.3 fs-usb bidirectional standard 3-pin mode table 6-89 and table 6-90 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-50 ). table 6-88. ls- / fs-usb timing conditions bidirectional standard 3-pin mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output condition c load output load capacitance (1) 15 pf (1) buffer strength configuration: lb0 = 1. table 6-89. ls- / fs-usb timing requirements bidirectional standard 3-pin mode (1) (2) no. parameter opp100 opp50 unit min max min max fsu19 t d(d,se0) time duration, mmx_txdat and mmx_txse0 low 14 14 ns together during transition fsu20 t d(d,se0) time duration, mmx_tsdat and mmx_txse0 high 8 8 ns together during transition (1) in mmx, x is equal to 0, 1, or 2. (2) see section 4.3.4 , processor clocks . 232 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 mmx_txen_n mmx_txdat mmx_txse0 mmx_rxrcv fsu16 fsu14 fsu15 fsu10 fsu10 fsu11 fsu11 fsu12 fsu13 fsu17 fsu18 transmit receive swps038-075
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-90. ls- / fs-usb switching characteristics bidirectional standard 3-pin mode (1) (2) no. parameter opp100 opp50 unit min max min max fsu21 t d(txenl-dv) delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns fsu22 t d(txenl-se0v) delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns fsu23 t s(d-se0) skew between mmx_txdat and mmx_txse0 transition 1.5 1.5 ns fsu24 t d(di-txenh) delay time, mmx_txdat invalid to mmx_txen_n high 81.8 81.8 ns fsu25 t d(se0i-txenh) delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 81.8 ns (1) in mmx, x is equal to 0, 1, or 2. (2) see section 4.3.4 , processor clocks . figure 6-50. ls- / fs-usb bidirectional standard 3-pin mode (1) (1) in mmx, x is equal to 0, 1, or 2. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 233 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-076 mmx_txen_n mmx_txdat mmx_txse0 fsu23 fsu21 fsu22 fsu19 fsu19 fsu20 fsu20 fsu24 fsu25 receive transmit
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.6.4 multiport high-speed universal serial bus (hs-usb) note for more information, see high-speed usb host subsystem and high-speed usb otg controller / high-speed usb otg controller and high-speed usb host subsystem and high-speed usb otg controller / high-speed usb host subsystem sections of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). in addition to the full-speed (fs) usb controller, a high-speed (hs) usb otg controller is incorporated in the device. it allows high-speed transactions (up to 480 mbit/s) on the usb ports 0, 1, 2, and 3 described below: ? port 0: C 12-bit slave mode (sdr) ? ports 1 and 2: C 12-bit master mode (sdr) ? port 3: 6.6.4.1 hsusb0 port 0 12-bit slave mode table 6-92 and table 6-93 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-51 ). table 6-91. hsusb0 timing conditions 12-bit slave mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output condition c load output load capacitance (1) 3.5 pf (1) buffer strength configuration: lb0 = 0. table 6-92. hsusb0 timing requirements 12-bit slave mode (3) (4) no. parameter opp100 unit min max hsu0 f p(clk) hsusb0_clk clock frequency (1) 60.03 mhz t j(clk) cycle jitter (2) , hsusb0_clk 500 ps hsu3 t s(dirv-clkh) setup time, hsusb0_dir valid before hsusb0_clk rising edge 6.68 ns t s(nxtv-clkh) setup time, hsusb0_nxt valid before hsusb0_clk rising edge 6.68 ns hsu4 t h(clkh-diriv) hold time, hsusb0_dir valid after hsusb0_clk rising edge 0 ns t h(clkh-nxt/iv) hold time, hsusb0_nxt valid after hsusb0_clk rising edge 0 ns hsu5 t s(datav-clkh) setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge 6.68 ns hsu6 t h(clkh-dativ) hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge 0 ns (1) related with the input maximum frequency supported by the usb module. (2) maximum cycle jitter supported by hsusb0_clk input clock (3) the timing requirements are assured up to the cycle jitter error condition specified. (4) see section 4.3.4 , processor clocks . 234 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-93. hsusb0 switching characteristics 12-bit slave mode (1) no. parameter opp100 unit min max hsu1 t d(clkl-stpv) delay time, hsusb0_clk high to output usb0_stp valid 8.6 ns t d(clkl-stpiv) delay time, hsusb0_clk high to output usb0_stp invalid 0 ns hsu2 t d(clkl-dv) delay time, hsusb0_clk high to output hsusb0_data[0:7] valid 8.6 ns t d(clkl-div) delay time, hsusb0_clk high to output hsusb0_data[0:7] invalid 0 ns (1) see section 4.3.4 , processor clocks . figure 6-51. hsusb0 12-bit slave mode 6.6.4.2 hsusb1 and hsusb2 ports 1 and 2 12-bit slave mode table 6-95 and table 6-96 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-52 ). table 6-94. hsusb1 and hsusb2 timing conditions 12-bit master mode timing condition parameter value unit input conditions t r input signal rise time 3 ns t f input signal fall time 2 ns output condition c load output load capacitance (1) 5 pf (1) buffer strength configuration: lb0 = 0. table 6-95. hsusb1 and hsusb2 timing requirements 12-bit master mode (1) (2) no. parameter opp100 unit min max hsu3 t su(dirv-clkh) setup time, input direction control hsusbx_dir valid before output clock 9.3 ns hsusbx_clk rising edge t su(nxtv-clkh) setup time, input next signal hsusbx_nxt valid before output clock 9.3 ns hsusbx_clk rising edge hsu4 t h(clkh-diriv) hold time, input direction control hsusbx_dir valid after output clock C 0.52 ns hsusbx_clk rising edge t h(clkh-nxtiv) hold time, input next signal hsusbx_nxt valid after output clock C 0.52 ns hsusbx_clk rising edge hsu5 t su(dv-clkh) setup time, input data hsusbx_data[7:0] valid before output clock 9.3 ns hsusbx_clk rising edge copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 235 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-080 hsusb0_clk hsusb0_stp hsusb0_dir and hsusb0_nxt hsusb0_data[7:0] data_out data_in hsu1 hsu0 hsu1 hsu4 hsu2 hsu2 hsu6 hsu3 hsu5
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-95. hsusb1 and hsusb2 timing requirements 12-bit master mode (1) (2) (continued) no. parameter opp100 unit min max hsu6 t h(clkh-dv) hold time, input data hsusbx_data[7:0] valid after output clock C 0.52 ns hsusbx_clk rising edge (1) in hsusbx, x is equal to 1 or 2. (2) see section 4.3.4 , processor clocks . table 6-96. hsusb1 and hsusb2 switching characteristics 12-bit master mode (1) (3) no. parameter opp100 unit min max hsu0 f p(clk) frequency, output clock hsusbx_clk 60 mhz t j(clk) jitter standard deviation (2) , output clock hsusbx_clk 400 ps hsu1 t d(clkh-stpv) delay time, output clock hsusbx_clk rising edge to output stop signal 12.81 ns hsusbx_stp valid t d(clkh-stpiv) delay time, output clock hsusbx_clk rising edge to output stop signal 1.95 ns hsusbx_stp invalid hsu2 t d(clkh-dv) delay time, output clock hsusbx_clk rising edge to output data 12.81 ns hsusbx_data[7:0] valid t d(clkh-div) delay time, output clock hsusbx_clk rising edge to output data 1.95 ns hsusbx_data[7:0] invalid t r(d) rise time, output data hsusbx_data[7:0] 0 ns t f(d) fall time, output data hsusbx_data[7:0] 0 ns (1) in hsusbx, x is equal to 1 or 2. (2) the jitter probability density can be approximated by a gaussian function. (3) see section 4.3.4 , processor clocks . (1) in hsusbx, x is equal to 1 or 2. figure 6-52. hsusb1 and hsusb2 12-bit master mode 6.6.5 inter-integrated circuit interface (i 2 c) note for more information, see multimaster high-speed i2c controller chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the multi-master i 2 c peripheral provides an interface between two or more devices via an i 2 c serial bus. 236 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-081 hsusbx_clk hsusbx_stp hsusbx_dir and hsusbx_nxt hsusbx_data[7:0] data_out data_in hsu1 hsu0 hsu1 hsu4 hsu2 hsu2 hsu6 hsu3 hsu5
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 the i 2 c controller supports the multi-master mode which allows more than one device capable of controlling the bus to be connected to it. each i 2 c device is recognized by a unique address and can operates as either transmitter or receiver, according to the function of the device. in addition to being a transmitter or receiver, a device connected to the i 2 c bus can also be considered as master or slave when performing data transfers. this data transfer is carried out via two serial bidirectional wires: ? an sda data line ? an scl clock line in figure 6-53 the data transfer is in master or slave configuration with 7-bit addressing format. the i 2 c interface is compliant with philips i 2 c specification version 2.1. it supports standard mode (up to 100k bits/s), fast mode (up to 400k bits/s) and high-speed mode (up to 3.4mb/s). 6.6.5.1 i 2 c standard and fast modes table 6-97. i 2 c standard and fast modes no. parameter standard mode fast mode unit min max min max f scl frequency, clock i2cx_scl (4) 100 400 khz i1 t w(sclh) pulse duration, clock i2cx_scl (4) high 4.0 0.6 s i2 t w(scll) pulse duration, clock i2cx_scl (4) low 4.7 1.3 s i3 t su(sdav-sclh) setup time, data i2cx_sda (4) valid before clock 250 100 (1) ns i2cx_scl (4) active level i4 t h(sclh-sdav) hold time, data i2cx_sda (4) valid after clock 0 (2) 3.45 (3) 0 (2) 0.9 (3) s i2cx_scl (4) active level i5 t su(sdal-sclh) setup time, clock i2cx_scl (4) high after data 4.7 0.6 s i2cx_sda (4) low (for a start (5) condition or a repeated start condition) i6 t h(sclh-sdah) hold time, data i2cx_sda low level after clock 4.0 0.6 s i2cx_scl (4) high level (stop condition) i7 t h(sclh-rstart) hold time, data i2cx_sda (4) low level after 4.0 0.6 s clock i2cx_scl (4) high level (for a repeated start condition) i8 t w(sdah) pulse duration, data i2cx_sda (4) high between 4.7 (4) 1.3 s stop and start conditions t r(scl) rise time, clock i2cx_scl (4) 1000 20 + 300 ns 0.1c b t f(scl) fall time, clock i2cx_scl (4) 300 20 + 300 ns 0.1c b t r(sda) rise time, data i2cx_sda (4) 1000 20 + 300 ns 0.1c b t f(sda) fall time, data i2cx_sda (4) 300 20 + 300 ns 0.1c b c b capacitive load for each bus line 400 400 pf (1) a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su(sdav-sclh) 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the i2cx_scl (4) . if such a device does stretch the low period of the i2cx_scl (4) , it must output the next data bit to the i2cx_sda (4) line t r(sda) max + t su(sdav-sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the i2cx_scl (4) line is released. (2) the device provides (via the i 2 c bus) a minimum hold time (= i2c_fclk period x (psc+1) x 4) for the i2cx_sda (4) signal (see the fall and rise times of i2cx_scl (4) ) to bridge the undefined region of the falling edge of i2cx_scl (4) . (3) the maximum t h(sclh-sda) has only to be met if the device does not stretch the low period of the i2cx_scl (4) signal. (4) in i2cx, x is equal to 1, 2, 3, or 4. note that i2c4 is master transmitter only. (5) after this time, the first clock is generated. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 237 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in i2cx, x is equal to 1, 2, 3, or 4. figure 6-53. i 2 c standard and fast modes 6.6.5.2 i 2 c high-speed mode table 6-98. i 2 c high-speed mode no. parameter min max unit f scl frequency, clock i2cx_scl (3) 3.4 (5) mhz i1 t w(sclh) pulse duration, clock i2cx_scl (3) high 60 (1) ns i2 t w(scll) pulse duration, clock i2cx_scl (3) low 160 (1) ns i3 t su(sdav-sclh) setup time, data i2cx_sda (3) valid before clock i2cx_scl (3) active level 10 ns i4 t h(sclh-sdav) hold time, data i2cx_sda (3) valid after clock i2cx_scl (3) active level 0 (4) 70 ns i5 t su(sdal-sclh) setup time, clock i2cx_scl (3) high after data i2cx_sda (3) low (for a 160 ns start (2) condition or a repeated start condition) i6 t h(sclh-sdah) hold time, data i2cx_sda (3) low level after clock i2cx_scl (3) high level 160 ns (stop condition) i7 t h(sclh-rstart) hold time, data i2cx_sda (3) low level after clock i2cx_scl (3) high level 160 ns (for a repeated start condition) t r(scl) rise time, clock i2cx_scl (3) 10 40 ns t r(scl) rise time, clock i2cx_scl (3) after a repeated start condition and after 10 80 ns a bit acknowledge t f(scl) fall time, clock i2cx_scl (3) 10 40 ns t r(sda) rise time, data i2cx_sda (3) 10 80 ns t f(sda) fall time, data i2cx_sda (3) 10 80 ns c b capacitive load for each bus line 100 pf (1) hs-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t w(scll) > 2 * t w(sclh) . (2) after this time, the first clock is generated. (3) in i2cx, x is equal to 1, 2, 3, or 4. note that i2c4 is master transmitter only. (4) the device provides (via the i 2 c bus) a minimum hold time (= i2c_fclk period x 4) for the i2cx_sda (3) signal (see the fall and rise times of i2cx_scl (3) ) to bridge the undefined region of the falling edge of i2cx_scl (3) . (5) the i2c4 clock frequency in high-speed mode is equal to the sys_xtalin input clock frequency divided by 15. (1) in i2cx, x is equal to 1, 2, 3, or 4. figure 6-54. i 2 c high-speed mode 238 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-084 i2cx_sda i2cx_scl start repeat stop start start i1 i2 i3 i4 i5 i6 i6 i7 i8 swps038-085 i2cx_sda i2cx_scl stop start repeat ih1 ih2 ih3 ih4 ih6 ih5 ih7
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-99. i 2 c correspondence standard vs data manual timing references ti standard-i 2 c standard/fast modes high-speed mode f scl f scl f sclh i1 t w(sclh) t high t high i2 t w(scll) t low t low i3 t su(sdav-sclh) t su;dat t su;dat i4 t h(sclh-sdav) t su;dat t su;dat i5 t su(sdal-sclh) t su;sta t su;sta i6 t h(sclh-sdah) t hd;sta t hd;sta i7 t h(sclh-rstart) t su;sto t su;sto i8 t w(sdah) t buf 6.6.6 hdq / 1-wire interface (hdq/1-wire) note for more information, see hdq/1-wire / hdq/1-wire chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the module is intended to work with both hdq and 1-wire protocols. the protocols use a single wire to communicate between the master and the slave. the protocols employ an asynchronous return to one mechanism where, after any command, the line is pulled high. 6.6.6.1 hdq/1-wire hdq mode table 6-100 and table 6-102 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-55 through figure 6-59 ). table 6-100. hdq interface read timing parameter description min typ max unit t cych read bit window timing 190 250 s t hw1 read one data valid after hdq low 32 (2) 66 (2) s t hw0 read zero data hold after hdq low 70 (2) 145 (2) s t rsps response time from hdq slave device (1) 190 320 s (1) defined by software (2) if the hdq slave device drives a logic-low state after t hw0 max, it can be interpreted as a break pulse. for more information see table 6-101 and the hdq/1-wire chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). table 6-101. hdq sampling cases (1) cases first sampling (at 68 s) second sampling (at 180 s) 1 l (logic-low state) l (logic-low state) 2 l (logic-low state) h (logic-high state) 3 h (logic-high state) l (logic-low state) 4 h (logic-high state) h (logic-high state) (1) the different cases can be interpreted as follows: C case 1: if a logic-low state is present at the first sampling time and also at the second sampling time, the receive data can be interpreted as a break pulse. C case 2: if a logic-low state is present at the first sampling time and a logic-high state is present at the second sampling time, the receive data on the line is a zero (data). C case 3: undefined. C case 4: if a logic-high state is present at the first sampling time and also at the second sampling time, the receive data on the line is a one (data). copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 239 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-102. hdq write switching characteristics parameter description min typ max unit t b break timing 190 s t br break recovery time 40 s t cycd write bit windows timing 190 s t dw1 write one data valid after hdq low 0.5 50 s t dw0 write zero data hold after hdq low 86 145 s figure 6-55. hdq break and break recovery timing hdq interface writing to slave figure 6-56. hdq break detection hdq interface reading slave figure 6-57. hdq interface bit read timing (data) figure 6-58. hdq interface bit write timing (command/address or data) figure 6-59. hdq communication 6.6.6.2 hdq/1-wire 1-wire mode table 6-103 and table 6-104 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-60 through figure 6-63 ). 240 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-086 hdq t b t br hdq first sampling time second sampling time t hw1 t hw0 t b t br swps038-122 swps038-087 hdq t hw1 t hw0 t cych swps038-088 hdq t dw1 t dw0 t cycd swps038-089 hdq break 0_(lsb) 1 6 7_(msb) t rsps 1 6 command_byte_written data_byte_received 0_(lsb)
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-103. hdq/1-wire timing requirements 1-wire mode parameter description min typ max unit t pdh presence pulse delay high 15 60 s t pdl presence pulse delay low 60 240 s t rdv read data valid time t lowr 15 s t rel read data release time 0 45 s table 6-104. hdq/1-wire switching characteristics 1-wire mode parameter description min typ max unit t rstl reset time low 480 960 s t rsth reset time high 480 s t slot bit cycle time 60 120 s t low1 write bit-one time 1 15 s t low0 write bit-zero time (2) 60 120 s t rec recovery time 1 s t lowr read bit strobe time (1) 1 15 s (1) t lowr (low pulse sent by the master) must be short as possible to maximize the master sampling window. (2) t low0 must be less than t slot . figure 6-60. 1-wire reset timing figure 6-61. 1-wire read bit timing (data) figure 6-62. 1-wire write bit-one timing (command / address or data) figure 6-63. 1-wire write bit-zero timing (command/address or data) copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 241 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-091 1-wire t lowr t rel t slot t rdv t rec 1-wire t low1 t slot t rec swps038-123 1-wire t low0 t slot t rec swps038-124 swps038-090 1-wire t rsth t pdl t pdh t rtsl
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.6.7 universal asynchronous receiver transmitter (uart) note for more information, see uart/irda/cir chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). 6.6.7.1 uart table 6-105. uart switching characteristics (2) signal name mux mode description min max unit universal asynchronous receiver/transmitter (uart1) uart1 (uart1_tx): aa8 0 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart1 (uart1_rts): aa9 0 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart1 (uart1_tx): e26 2 t r , rise time 0.6 2.4 ns t f , fall time c l , output load 2 22 pf uart1 (uart1_rts): ah22 2 t r , rise time sc0, sc1 = 00 (1) 1 15 ns t f , fall time c l , output load 4 60 pf t r , rise time sc0, sc1 = 00 (1) 0.4 5 ns t f , fall time c l , output load 2 21 pf t r , rise time sc0, sc1 = 00 (1) 0.6 7 ns t f , fall time c l , output load 7 33 pf universal asynchronous receiver/transmitter (uart2) uart2 (uart2_tx): aa25 0 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart2 (uart2_rts): ab25 0 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart2 (uart2_tx): af5 1 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart2 (uart2_rts): ae6 1 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart2 (uart2_tx): t27 5 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart2 (uart2_rts): u27 5 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf universal asynchronous receiver/transmitter (uart3) 242 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-105. uart switching characteristics (2) (continued) signal name mux mode description min max unit uart3 (uart3_cts_rctx): h18 0 t r , rise time sc0, sc1 = 00 (1) 1 15 ns t f , fall time c l , output load 4 60 pf t r , rise time sc0, sc1 = 00 (1) 0.4 5 ns t f , fall time c l , output load 2 21 pf t r , rise time sc0, sc1 = 00 (1) 0.6 7 ns t f , fall time c l , output load 7 33 pf uart3 (uart3_rts_sd): h19 0 t r , rise time sc0, sc1 = 00 (1) 1 15 ns t f , fall time c l , output load 4 60 pf t r , rise time sc0, sc1 = 00 (1) 0.4 5 ns t f , fall time c l , output load 2 21 pf t r , rise time sc0, sc1 = 00 (1) 0.6 7 ns t f , fall time c l , output load 7 33 pf uart3 (uart3_tx_irtx): h21 0 t r , rise time sc0, sc1 = 00 (1) 1 15 ns t f , fall time c l , output load 4 60 pf t r , rise time sc0, sc1 = 00 (1) 0.4 5 ns t f , fall time c l , output load 2 21 pf t r , rise time sc0, sc1 = 00 (1) 0.6 7 ns t f , fall time c l , output load 7 33 pf uart3 (uart3_cts_rctx): u26 2 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart3 (uart3_rts_sd): u27 2 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf uart3 (uart3_tx_irtx): ah24 2 t r , rise time sc0, sc1 = 00 (1) 1 15 ns t f , fall time c l , output load 4 60 pf t r , rise time sc0, sc1 = 00 (1) 0.4 5 ns t f , fall time c l , output load 2 21 pf t r , rise time sc0, sc1 = 00 (1) 0.6 7 ns t f , fall time c l , output load 7 33 pf uart3 (uart3_tx_irtx): g26 2 t r , rise time 0.6 2.4 ns t f , fall time c l , output load 2 22 pf copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 243 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-105. uart switching characteristics (2) (continued) signal name mux mode description min max unit uart3 (uart3_tx_irtx): t27 2 t r , rise time 1.5 5.5 ns t f , fall time c l , output load 2 22 pf universal asynchronous receiver/transmitter (uart4) uart4 (uart4_tx): k8 2 t r , rise time 0.6 2.4 ns t f , fall time c l , output load 2 22 pf (1) the mode is configured by bits sc0 and sc1 of the io cell. for more details, see the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (2) caution: up to a rise time or a fall time of 1.2 ns, this can create emi parasitics. 6.6.7.2 uart3 irda the irda module can operate in three different modes: ? slow infrared (sir) ( 115.2 kbits/s) ? medium infrared (mir) (0.576 mbits/s and 1.152 mbits/s) ? fast infrared (fir) (4 mbits/s) figure 6-64. uart irda pulse parameters 6.6.7.2.1 uart3 irda receive mode table 6-106. uart3 irda signaling rate and pulse duration receive mode signaling rate electrical pulse duration unit min typ max sir 2.4 kbit/s 52.17 78.13 208.33 s 9.6 kbit/s 13.10 19.53 52.08 s 19.2 kbit/s 6.59 9.77 26.04 s 38.4 kbit/s 3.34 4.88 13.02 s 57.6 kbit/s 2.25 3.26 8.68 s 115.2 kbit/s 1.17 1.63 4.34 s mir 0.576 mbit/s 300.55 416.67 867.86 ns 244 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-093 pulse duration 90% 90% 50% 50% 10% 10% t r t f
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-106. uart3 irda signaling rate and pulse duration receive mode (continued) signaling rate electrical pulse duration unit min typ max 1.152 mbit/s 192.04 208.33 433.83 ns fir 4.0 mbit/s (single pulse) 62.70 125.00 170.63 ns 4.0 mbit/s (double pulse) 208.53 250.00 291.47 ns table 6-107. uart3 irda rise and fall times receive mode parameter min typ max unit t r rise time, input data uart3_rx_irrx 200 ns t f fall time, input data uart3_rx_irrx 200 ns 6.6.7.2.2 uart3 irda transmit mode table 6-108. uart3 irda signaling rate and pulse duration transmit mode signaling rate electrical pulse duration unit min typ max sir 2.4 kbit/s 78.1 78.1 78.1 s 9.6 kbit/s 19.5 19.5 19.5 s 19.2 kbit/s 9.75 9.75 9.75 s 38.4 kbit/s 4.87 4.87 4.87 s 57.6 kbit/s 3.25 3.25 3.25 s 115.2 kbit/s 1.62 1.62 1.62 s mir 0.576 mbit/s 414 416 419 ns 1.152 mbit/s 206 208 211 ns fir 4.0 mbit/s (single pulse) 123 125 128 ns 4.0 mbit/s (double pulse) 248 250 253 ns 6.6.8 removable media interfaces 6.6.8.1 multimedia memory card and secure digital io card (mmc) note for more information, see mmc/sd/sdio card interface chapter of the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). the mmc host controller provides an interface to high-speed and standard mmc, sd memory cards, or sdio cards. the application interface is responsible for managing transaction semantics. the mmc/sdio host controller deals with mmc/sdio protocol at transmission level, packing data, adding crc, start/end bit, and checking for syntactical correctness. there are three mmc interfaces on the device: ? mmc1: C 1.8-v / 3-v support C 4-bit in standard mmc, high-speed mmc, standard sd, and high-speed sd modes copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 245 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com ? mmc2: C 1.8-v support C 8-bit without external transceiver C 4-bit with external transceiver allowing supporting 3-v peripherals. transceiver direction control signals are multiplexed with the upper four data bits. ? mmc3: C 1.8-v support C 8-bit without external transceiver 6.6.8.1.1 mmc1 interface sd identification modes table 6-110 and table 6-111 assume testing over the recommended operating conditions and electrical characteristic conditions below. table 6-109. mmc1 interface timing conditions sd identification modes timing condition parameter value unit input conditions t r input signal rise time 10 ns t f input signal fall time 10 ns output condition c load output load capacitance (1) 40 pf (1) buffer strength configuration: lb0 = 0. table 6-110. mmc1 interface timing requirements sd identification modes (1) (2) no. parameter opp100 opp50 unit min max min max mmc1 interface (1.8-v io) sd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 1198.4 1198.4 ns clock edge sd4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 1249.2 1249.2 ns clock edge mmc1 interface (3.0-v io) sd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 1198.4 1198.4 ns clock edge sd4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 1249.2 1249.2 ns clock edge (1) corresponding figures showing timing parameters are common with other interface modes. (see sd , hs sd modes). (2) see section 4.3.4 , processor clocks . table 6-111. mmc1 interface switching characteristics sd identification modes (4) (7) no. parameter opp100 opp50 unit min max min max sd identification mode sd1 t c(clk) frequency (1) , output clock period 0.4 0.4 mhz sd2 t w(clkh) typical pulse duration, output clock high x (5) *po (2) x (5) *po (2) ns sd2 t w(clkl) typical pulse duration, output clock low y (6) *po (2) y (6) *po (2) ns t dc(clk) duty cycle error, output clock 125 125 ns t j(clk) jitter standard deviation (3) , output clock 200 200 ps mmc1 interface (1.8-v io) t r(clk) rise time, output clock 10 10 ns t f(clk) fall time, output clock 10 10 ns 246 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-111. mmc1 interface switching characteristics sd identification modes (4) (7) (continued) no. parameter opp100 opp50 unit min max min max t r(data) rise time, output data 10 10 ns t f(data) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 6.3 2492.7 6.3 2492.7 ns transition mmc1 interface (3.0-v io) t r(clk) rise time, output clock 10 10 ns t f(clk) fall time, output clock 10 10 ns t r(data) rise time, output data 10 10 ns t f(data) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 6.3 2492.7 6.3 2492.7 ns transition (1) related with the output clock maximum and minimum frequencies programmable in mmc module. (2) po = output clock period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) corresponding figures showing timing parameters are common with other interface modes. (see sd, hs sd modes). (5) the x parameter is defined as follows: clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) the y parameter is defined as follows: clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (7) see section 4.3.4 , processor clocks . 6.6.8.1.2 mmc1 interface high-speed sd mode table 6-113 and table 6-114 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-65 and figure 6-66 ). table 6-112. mmc1 interface timing conditions high-speed sd mode timing condition parameter value unit input conditions t r input signal rise time 3 ns t f input signal fall time 3 ns output condition c load output load capacitance (1) 40 pf (1) buffer strength configuration: speedctrl = 1. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 247 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-113. mmc1 interface timing requirements high-speed sd mode (2) no. parameter opp100 opp50 unit min max min max mmc1 interface (1.8-v io) hssd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 5.6 26 ns clock edge hssd4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 2.3 1.9 ns clock edge hssd7 t su(datxv-clkih) setup time, mmc1_dat[n:0] (1) valid before mmc1_clk 5.6 26 ns rising clock edge hssd8 t h(clkih-datxiv) hold time, mmc1_dat[n:0] (1) valid after mmc1_clk 2.3 1.9 ns rising clock edge mmc1 interface (3.0-v io) hssd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 5.6 26 ns clock edge hssd4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 2.3 1.9 ns clock edge hssd7 t su(datxv-clkih) setup time, mmc1_dat[n:0] (1) valid before mmc1_clk 5.6 26 ns rising clock edge hssd8 t h(clkih-datxiv) hold time, mmc1_dat[n:0] (1) valid after mmc1_clk 2.3 1.9 ns rising clock edge (1) in mmc1_dat[n:0], n is equal to 3. (2) see section 4.3.4 , processor clocks . 248 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-114. mmc1 interface switching characteristics high-speed sd mode (7) no. parameter opp100 opp50 unit min max min max high-speed sd mode hssd1 t c(clk) frequency (1) , output clock period 48 24 mhz hssd2 t w(clkh) typical pulse duration, output clock high x (4) *po (2) x (4) *po (2) ns hssd2 t w(clkl) typical pulse duration, output clock low y (5) *po (2) y (5) *po (2) ns t dc(clk) duty cycle error, output clock 1041.67 2083.33 ps t j(clk) jitter standard deviation (3) , output clock 200 200 ps mmc1 interface (1.8-v io) t r(clk) rise time, output clock 3 3 ns t f(clk) fall time, output clock 3 3 ns t r(data) rise time, output data 3 3 ns t f(data) fall time, output data 3 3 ns hssd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 3.72 14.11 4.13 34.53 ns transition hssd6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 3.72 14.11 4.13 34.53 ns mmc1_dat[n:0] (6) transition mmc1 interface (3.0-v io) t r(clk) rise time, output clock 3 3 ns t f(clk) fall time, output clock 3 3 ns t r(data) rise time, output data 3 3 ns t f(data) fall time, output data 3 3 ns hssd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 3.72 14.11 4.13 34.53 ns transition hssd6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 3.72 14.11 4.13 34.53 ns mmc1_dat[n:0] (6) transition (1) related with the output clock maximum and minimum frequencies programmable in mmc module. (2) po = output clock period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) the x parameter is defined as follows: clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (5) the y parameter is defined as follows: clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) in mmc1_dat[n:0], n is equal to 3. (7) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 249 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 6-65. mmc1 interface high-speed sd mode data/command receive figure 6-66. mmc1 interface high-speed sd mode data/command transmit 6.6.8.1.3 mmc1 interface standard sd mode table 6-116 and table 6-117 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-67 and figure 6-68 ). table 6-115. mmc1 interface timing conditions standard sd mode timing condition parameter value unit input conditions t r input signal rise time 10 ns t f input signal fall time 10 ns output condition c load output load capacitance (1) 40 pf (1) buffer strength configuration: speedctrl = 1. table 6-116. mmc1 interface timing requirements standard sd mode (1) (2) (4) no. parameter opp100 opp50 unit min max min max mmc1 interface (1.8-v io) sd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 3.3 21.9 ns clock edge sd4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 18.1 36.7 ns clock edge sd7 t su(datxv-clkih) setup time, mmc1_dat[n:0] (3) valid before mmc1_clk 3.3 21.9 ns rising clock edge sd8 t h(clkih-datxiv) hold time, mmc1_dat[n:0] (3) valid after mmc1_clk 18.1 36.7 ns rising clock edge mmc1 interface (3.0-v io) sd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 3.3 21.9 ns clock edge 250 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-094 mmc1_clk mmc1_cmd mmc1_dat[3:0] hssd3 hssd7 hssd4 hssd8 hssd1 hssd2 swps038-095 mmc1_clk mmc1_cmd mmc1_dat[3:0] hssd5 hssd5 hssd6 hssd6 hssd1 hssd2
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-116. mmc1 interface timing requirements standard sd mode (1) (2) (4) (continued) no. parameter opp100 opp50 unit min max min max sd4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 18.1 36.7 ns clock edge sd7 t su(datxv-clkih) setup time, mmc1_dat[n:0] (3) valid before mmc1_clk 3.3 21.9 ns rising clock edge sd8 t h(clkih-datxiv) hold time, mmc1_dat[n:0] (3) valid after mmc1_clk 18.1 36.7 ns rising clock edge (1) timing parameters are referred to output clock specified in table 6-117 . (2) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified in table 6-117 . (3) in mmc1_dat[n:0], n is equal to 3. (4) see section 4.3.4 , processor clocks . table 6-117. mmc1 interface switching characteristics standard sd mode (7) no. parameter opp100 opp50 unit min max min max standard sd mode sd1 t c(clk) frequency (1) , output clock period 24 12 mhz sd2 t w(clkh) typical pulse duration, output clock high x (4) *po (2) x (4) *po (2) ns sd2 t w(clkl) typical pulse duration, output clock low y (5) *po (2) y (5) *po (2) ns t dc(clk) duty cycle error, output clock 2083.33 4166.67 ps t j(clk) jitter standard deviation (3) , output clock 200 200 ps mmc1 interface (1.8-v) t r(clk) rise time, output clock 10 10 ns t f(clk) fall time, output clock 10 10 ns t r(data) rise time, output data 10 10 ns t f(data) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 6.13 35.53 6.3 77.03 ns transition sd6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 6.13 35.53 6.3 77.03 ns mmc1_dat[n:0] (6) transition mmc1 interface (3.0-v) t r(clk) rise time, output clock 10 10 ns t f(clk) fall time, output clock 10 10 ns t r(data) rise time, output data 10 10 ns t f(data) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 6.13 35.53 6.3 77.03 ns transition sd6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 6.13 35.53 6.3 77.03 ns mmc1_dat[n:0] (6) transition (1) related with the output clock maximum and minimum frequencies programmable in mmc module. (2) po = output clock period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) the x parameter is defined as follows: clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 251 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (5) the y parameter is defined as follows: clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) in mmc1_dat[n:0], n is equal to 3. (7) see section 4.3.4 , processor clocks . figure 6-67. mmc1 interface standard sd mode data/command receive figure 6-68. mmc1 interface standard sd mode data/command transmit 6.6.8.1.4 mmc1 interface standard mmc and mmc identification modes table 6-119 and table 6-120 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-69 and figure 6-70 ). 252 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-098 mmc1_clk mmc1_cmd mmc1_dat[n:0] sd3 sd7 sd4 sd8 sd1 sd2 swps038-099 mmc1_clk mmc1_cmd mmc1_dat[n:0] sd1 sd2 sd5 sd6 sd5 sd6
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-118. mmc1 interface timing conditions standard mmc and mmc identification modes timing condition parameter value unit input conditions t r input signal rise time 3 ns t f input signal fall time 3 ns output conditions c load output load capacitance (1) 30 pf (1) buffer strength configuration: speedctrl = 1. table 6-119. mmc1 interface timing requirements standard mmc and mmc identification modes (2) (3) (4) no. parameter opp100 opp50 unit min max min max mmc1 interface (1.8-v io) mmc3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 13.6 55.1 ns clock edge mmc4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 7.7 7.5 ns clock edge mmc7 t su(datxv-clkih) setup time, mmc1_dat[n:0] (1) valid before mmc1_clk 13.6 55.1 ns rising clock edge mmc8 t h(clkih-datxiv) hold time, mmc1_dat[n:0] (1) valid after mmc1_clk 7.7 7.5 ns rising clock edge mmc1 interface (3.0-v io) mmc3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 13.6 55.1 ns clock edge mmc4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 7.7 7.5 ns clock edge mmc7 t su(datxv-clkih) setup time, mmc1_dat[n:0] (1) valid before mmc1_clk 13.6 55.1 ns rising clock edge mmc8 t h(clkih-datxiv) hold time, mmc1_dat[n:0] (1) valid after mmc1_clk 7.7 7.5 ns rising clock edge (1) in mmc1_dat[n:0], n is equal to 3. (2) timing parameters are referred to output clock specified in table 6-120 . (3) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified in table 6-120 . (4) see section 4.3.4 , processor clocks . table 6-120. mmc1 interface switching characteristics standard mmc and mmc identification modes (7) no. parameter opp100 opp50 unit min max min max mmc identification mode mmc1 1/t c(clk) frequency (1) , output clk period 0.4 0.4 mhz mmc2 t w(clkh) typical pulse duration, output clk high x (5) *po (2) x (5) *po (2) ns mmc2 t w(clkl) typical pulse duration, output clk low y (6) *po (2) y (6) *po (2) ns t dc(clk) duty cycle error, output clk 125 125 ns t j(clk) jitter standard deviation (3) , output clk 200 200 ps standard mmc identification mode mmc1 t c(clk) frequency (1) , output clk period 24 12 mhz mmc2 t w(clkh) typical pulse duration, output clk high x (5) *po (2) x (5) *po (2) ns mmc2 t w(clkl) typical pulse duration, output clk low y (6) *po (2) y (6) *po (2) ns t dc(clk) duty cycle error, output clk 2083.3 4166.7 ps t j(clk) jitter standard deviation (3) , output clk 200 200 ps mmc1 interface (1.8-v io) t r(clk) rise time, output clk 10 10 ns copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 253 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-120. mmc1 interface switching characteristics standard mmc and mmc identification modes (7) (continued) no. parameter opp100 opp50 unit min max min max t f(clk) fall time, output clk 10 10 ns t r(data) rise time, output data 10 10 ns t f(data) fall time, output data 10 10 ns mmc5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 4.1 37.6 4.3 79 ns transition mmc6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 4.1 37.6 4.3 79 ns mmc1_dat[n:0] (4) transition mmc1 interface (3.0-v io) t r(clk) rise time, output clk 10 10 ns t f(clk) fall time, output clk 10 10 ns t r(data) rise time, output data 10 10 ns t f(data) fall time, output data 10 10 ns mmc5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 4.1 37.6 4.3 79 ns transition mmc6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 4.1 37.6 4.3 79 ns mmc1_dat[n:0] (4) transition (1) related with the output clock maximum and minimum frequencies programmable in mmc module. (2) po = output clock period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) in mmc1_dat[n:0], n is equal to 3. (5) the x parameter is defined as follows: clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) the y parameter is defined as follows: clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (7) see section 4.3.4 , processor clocks . figure 6-69. mmc1 interface standard mmc and mmc identification modes data/command receive 254 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-102 mmc1_clk mmc1_cmd mmc1_dat[3:0] mmc3 mmc7 mmc4 mmc8 mmc1 mmc2
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 6-70. mmc1 interface standard mmc and mmc identification modes data/command transmit 6.6.8.1.5 mmc1 interface high-speed mmc mode table 6-122 and table 6-123 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-71 and figure 6-72 ). table 6-121. mmc1 interface timing conditions high-speed mmc mode timing condition parameter value unit input conditions t r input signal rise time 3 ns t f input signal fall time 3 ns output conditions c load output load capacitance (1) 30 pf (1) the load setting of the io buffer: speedctrl = 1. table 6-122. mmc1 interface timing requirements high-speed mmc mode (2) (3) (4) (5) no. parameter opp100 opp50 unit min max min max mmc1 interface (1.8-v io) mmc3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 5.6 26.0 ns clock edge mmc4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 2.3 1.9 ns clock edge mmc7 t su(datxv-clkih) setup time, mmc1_dat[n:0] (1) valid before mmc1_clk 5.6 26.0 ns rising clock edge mmc8 t h(clkih-datxiv) hold time, mmc1_dat[n:0] (1) valid after mmc1_clk 2.3 1.9 ns rising clock edge mmc1 interface (3.0-v io) mmc3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk rising 5.6 26.0 ns clock edge mmc4 t h(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk rising 2.3 1.9 ns clock edge mmc7 t su(datxv-clkih) setup time, mmc1_dat[n:0] (1) valid before mmc1_clk 5.6 26.0 ns rising clock edge mmc8 t h(clkih-datxiv) hold time, mmc1_dat[n:0] (1) valid after mmc1_clk 2.3 1.9 ns rising clock edge (1) in mmc1_dat[n:0], n is equal to 3. (2) timing parameters are referred to output clock specified in table 6-123 . (3) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified in table 6-123 . (4) corresponding figures showing timing parameters are common with the standard mmc mode figures. (5) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 255 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-103 mmc1_clk mmc1_cmd mmc1_dat[3:0] mmc5 mmc5 mmc6 mmc6 mmc1 mmc2
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-123. mmc1 interface switching characteristics high-speed mmc mode (4) (8) no. parameter opp100 opp50 unit min max min max mmc1 t c(clk) frequency (1) , output clk period 48 24 mhz mmc2 t w(clkh) typical pulse duration, output clk high x (6) *po (2) x (6) *po (2) ns mmc2 t w(clkl) typical pulse duration, output clk low y (7) *po (2) y (7) *po (2) ns t dc(clk) duty cycle error, output clk 1041.7 2083.3 ps t j(clk) jitter standard deviation (3) , output clk 200 200 ps mmc1 interface (1.8-v io) t r(clk) rise time, output clk 3 3 ns t f(clk) fall time, output clk 3 3 ns t r(data) rise time, output data 3 3 ns t f(data) fall time, output data 3 3 ns mmc5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 3.7 14.1 4.1 34.5 ns transition mmc6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_dat[n:0] (5) transition mmc1 interface (3.0-v io) t r(clk) rise time, output clk 3 3 ns t f(clk) fall time, output clk 3 3 ns t r(data) rise time, output data 3 3 ns t f(clk) fall time, output data 3 3 ns mmc5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to mmc1_cmd 3.7 14.1 4.1 34.5 ns transition mmc6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_dat[n:0] (5) transition (1) related with the output clock maximum and minimum frequencies programmable in mmc module. (2) po = output clock period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) corresponding figures showing timing parameters are common with the standard mmc mode figures. (5) in mmc1_dat[n:0], n is equal to 3. (6) the x parameter is defined as follows: clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (7) the y parameter is defined as follows: clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (8) see section 4.3.4 , processor clocks . 256 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 figure 6-71. mmc1 interface high-speed mmc mode data/command receive figure 6-72. mmc1 interface high-speed mmc mode data/command transmit 6.6.8.1.6 mmc2 and mmc3 interfaces sdio identification mode table 6-125 and table 6-126 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-73 and figure 6-74 ). table 6-124. mmc2 and mmc3 interfaces timing conditions sdio identification mode timing condition parameter value unit input conditions t r input signal rise time 10 ns t f input signal fall time 10 ns output condition c load output load capacitance (1) 5 pf (1) buffer strength configuration: lb0 = 0 table 6-125. mmc2 and mmc3 interfaces timing requirements sdio identification mode (1) (2) no. parameter opp100 opp50 unit min max min max mmc2 and mmc3 interface (1.8-v io) sd3 t su(cmdv-clkih) setup time, mmcx_cmd valid before 1198.4 1198.4 ns mmcx_clk rising clock edge sd4 t h(clkih-cmdiv) hold time, mmcx_cmd valid after mmcx_clk 1249.2 1249.2 ns rising clock edge (1) see section 4.3.4 , processor clocks . (2) in mmcx, x is equal to 2 or 3. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 257 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-100 mmc1_clk mmc1_cmd mmc1_dat[3:0] mmc3 mmc7 mmc4 mmc8 mmc1 mmc2 swps038-101 mmc1_clk mmc1_cmd mmc1_dat[3:0] mmc5 mmc5 mmc6 mmc6 mmc1 mmc2
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com table 6-126. mmc2 and mmc3 interfaces switching characteristics sdio identification mode (4) (7) (7) no. parameter opp100 opp50 unit min max min max standard sdio mode sd1 t c(clk) frequency (1) , output clock period 0.4 0.4 mhz sd2 t w(clkh) typical pulse duration, output clock high x (5) * x (5) * ns po (2) po (2) sd2 t w(clkl) typical pulse duration, output clock low y (6) * y (6) * ns po (2) po (2) t dc(clk) duty cycle error, output clock 125 125 ns t j(clk) jitter standard deviation (3) , output clock 200 200 ps t r(clk) rise time, output clock 10 10 ns t f(clk) fall time, output clock 10 10 ns t r(data) rise time, output data 10 10 ns t f(data) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmcx_clk rising clock edge to 6.3 2492.7 6.3 77.03 ns mmcx_cmd transition (1) related to the output mmcx_clk maximum and minimum frequency. (2) p = output mmcx_clk period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) corresponding figures showing timing parameters are common with other interface modes (see sdio, hs sdio modes). (5) the x parameter is defined as follows: clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) the y parameter is defined as follows: clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (7) in mmcx, x is equal to 2 or 3. 6.6.8.1.7 mmc2 and mmc3 interfaces high-speed sdio mode table 6-128 and table 6-129 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-73 and figure 6-74 ). table 6-127. mmc2 and mmc3 interfaces timing conditions high-speed sdio mode timing condition parameter value unit min max input conditions t r input signal rise time 0.18 5.69 ns t f input signal fall time 0.19 5.70 ns output condition c load output load capacitance (1) 5 pf 258 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) buffer strength configuration for mmc2 and mmc3: lb0 = 0. table 6-128. mmc2 and mmc3 interfaces timing requirements high-speed sdio mode (2) no. parameter opp100 opp50 unit min max min max hssd3 t su(dv-clkh) setup time, mmcx_cmd valid before mmcx_clk rising 3.4 23.8 ns clock edge hssd4 t h(clkh-dv) hold time, mmcx_cmd valid after mmcx_clk rising 1.7 1.3 ns clock edge hssd7 t su(dv-clkh) setup time, mmcx_dat[n:0] (1) valid before mmcx_clk 3.4 23.8 ns rising clock edge hssd8 t h(clkh-dv) hold time, mmcx_dat[n:0] (1) valid after mmcx_clk rising 1.7 1.3 ns clock edge (1) in mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3. (2) see section 4.3.4 , processor clocks . table 6-129. mmc2 and mmc3 interfaces switching characteristics high-speed sdio mode (2) (5) no. parameter opp100 opp50 unit min max min max hssd1 t c(clk) frequency (1) , output mmcx_clk period 48 24 mhz hssd2 t w(clkh) typical pulse duration, output mmcx_clk high 0.5*p (3) 0.5*p (3) ns hssd2 t w(clkl) typical pulse duration, output mmcx_clk low 0.5*p (3) 0.5*p (3) ns t dc(clk) duty cycle error, output mmcx_clk C 1042 1042 C 2083 2083 ps t j(clk) jitter standard deviation (4) , output mmcx_clk C 65 65 C 65 65 ps hssd5 t d(clkl-dov) delay time, mmcx_clk rising clock edge to mmcx_cmd 2.6 13.8 3 34.3 ns transition hssd6 t d(clkl-dov) delay time, mmcx_clk rising clock edge to 2.6 13.8 3 34.3 ns mmcx_dat[n:0] (2) transition (1) related with the output mmcx_clk maximum and minimum frequency. (2) in mmcx, x = 2 or 3. in mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3. (3) p = output mmcx_clk period in ns. (4) the jitter probability density can be approximated by a gaussian function. (5) see section 4.3.4 , processor clocks . figure 6-73. mmc2 and mmc3 interfaces high-speed sdio mode data/command receive (1) (1) in mmcx, x = 2 or 3. in mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 259 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-096 mmcx_clk mmcx_cmd mmcx_dat[n:0] hssd4 hssd8 hssd3 hssd7 hssd1 hssd2 hssd2
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 6-74. mmc2 and mmc3 interfaces high-speed sdio mode data/command transmit (1) (1) in mmcx, x = 2 or 3. in mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3. 6.6.8.1.8 mmc2 and mmc3 interfaces standard sdio mode table 6-131 and table 6-132 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 5-89 and figure 5-90). table 6-130. mmc2 and mmc3 interfaces timing conditions standard sdio mode timing condition parameter value unit input conditions t r input signal rise time 10 ns t f input signal fall time 10 ns output condition c load output load capacitance (1) 5 pf (1) buffer strength configuration: speedctrl = 1 table 6-131. mmc2 and mmc3 interfaces timing requirements standard sdio mode (2) (3) no. parameter opp100 opp50 unit min max min max mmc2 and mmc3 interface (1.8-v io) sd3 t su(cmdv-clkih) setup time, mmcx_cmd valid before 3.3 21.9 ns mmcx_clk rising clock edge sd4 t h(clkih-cmdiv) hold time, mmcx_cmd valid after mmcx_clk 18.1 36.7 ns rising clock edge sd7 t su(datxv-clkih) setup time, mmcx_dat[n:0] (1) valid before 3.3 21.9 ns mmcx_clk rising clock edge sd8 t h(clkih-datxiv) hold time, mmcx_dat[n:0] (1) valid after 18.1 36.7 ns mmcx_clk rising clock edge (1) in mmcx_dat[n:0], n is equal to 3 for mmc2 and 7 for mmc3. (2) see section 4.3.4 , processor clocks . (3) in mmcx, x is equal to 2 or 3. table 6-132. mmc2 and mmc3 interfaces switching characteristics standard sdio mode (6) (7) no. parameter opp100 opp50 unit min max min max standard sdio mode sd1 t c(clk) frequency (1) , output clock period 24 12 mhz sd2 t w(clkh) typical pulse duration, output clock high x (4) * x (4) * ns po (2) po (2) sd2 t w(clkl) typical pulse duration, output clock low y (5) * y (5) * ns po (2) po (2) t dc(clk) duty cycle error, output clock 2083.33 4166.67 ps 260 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-097 mmcx_clk mmcx_cmd mmcx_dat[n:0] hssd5 hssd5 hssd6 hssd6 hssd1 hssd2 hssd2
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-132. mmc2 and mmc3 interfaces switching characteristics standard sdio mode (6) (7) (continued) no. parameter opp100 opp50 unit min max min max t j(clk) jitter standard deviation (3) , output clock 200 200 ps t r(clk) rise time, output clock 10 10 ns t f(clk) fall time, output clock 10 10 ns t r(data) rise time, output data 10 10 ns t f(data) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmcx_clk rising clock edge to 6.13 35.53 6.3 77.03 ns mmcx_cmd transition sd6 t d(clkoh-datx) delay time, mmcx_clk rising clock edge to 6.13 35.53 6.3 77.03 ns mmcx_dat[n:0] (6) transition (1) related to the output mmcx_clk maximum and minimum frequency. (2) p = output mmcx_clk period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) the x parameter is defined as follows: clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (5) the y parameter is defined as follows: clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd all required details about clock division factor clkd can be found in the am/dm37x multimedia device technical reference manual (literature number sprugn4 ). (6) in mmcx, x is equal to 2 or 3. in mmcx_dat[n :0] is equal to 3 for mmc2 and 7 for mmc3. (7) see section 4.3.4 , processor clocks . figure 6-75. mmc2 and mmc3 interfaces standard sdio mode data/command receive (1) (1) in mmcx, x is equal to 2 or 3. in mmcx_dat[n:0] is equal to 3 for mmc2 and 7 for mmc3. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 261 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-098 mmc1_clk mmc1_cmd mmc1_dat[n:0] sd3 sd7 sd4 sd8 sd1 sd2
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com figure 6-76. mmc2 and mmc3 interfaces standard sdio mode data/command transmit (1) (1) in mmcx, x is equal to 2 or 3. in mmcx_dat[n:0] is equal to 3 for mmc2 and 7 for mmc3. 6.6.8.1.9 mmc2 and mmc3 interfaces embedded media interface (emmc) high-speed jc64 mode table 6-134 and table 6-135 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-77 through figure 6-78 ). table 6-133. mmc2 and mmc3 interfaces timing conditions high-speed jc64 mode timing condition parameter value unit min max input conditions t r input signal rise time 0.38 3.82 ns t f input signal fall time 0.39 3.68 ns output condition c load output load capacitance (1) 14 pf (1) buffer strength configuration for mmc3: lb0 = 1. table 6-134. mmc2 and mmc3 interfaces timing requirements high-speed jc64 mode (1) no. parameter opp100 opp50 unit min max min max mmc3 t su(cmdv-clkh) setup time, input command mmcx_cmd valid before 5.1 25.5 ns output clock mmcx_clk rising edge mmc4 t h(clkh-cmdiv) hold time, input command mmcx_cmd valid after 1.3 0.9 ns output clock mmcx_clk rising edge mmc7 t su(dv-clkh) setup time, input data mmcx_dat[n:0] valid before 5.1 25.5 ns output clock mmcx_clk rising edge mmc8 t h(clkh-div) hold time, input data mmcx_dat[n:0] valid after output 1.3 0.9 ns clock mmcx_clk rising edge (1) in mmx_dat[n:0], x is equal to 2 or 3 and n is equal to 7. (2) in mmx_cmd, x is equal to 2 or 3. (3) in mmx_clk, x is equal to 2 or 3. table 6-135. mmc2 and mmc3 interfaces switching characteristics high-speed jc64 mode (5) (6) (7) no. parameter opp100 opp50 unit min max min max mmc1 1/t c(clk) frequency (1) , output mmcx_clk period 48 24 mhz mmc2 t w(clkh) typical pulse duration, output mmcx_clk high 0.5*p (2) 0.5*p (2) ns mmc2 t w(clkl) typical pulse duration, output mmcx_clk low 0.5*p (2) 0.5*p (2) ns t dc(clk) duty cycle error, output mmcx_clk C 1042 1042 C 2083 2083 ps t j(clk) jitter standard deviation (3) , output mmcx_clk C 65 65 C 65 65 ps t r(clk) rising time, output mmcx_clk 2263 2263 ps t f(clk) falling time, output mmcx_clk 2136 2136 ps 262 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-099 mmc1_clk mmc1_cmd mmc1_dat[n:0] sd1 sd2 sd5 sd6 sd5 sd6
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-135. mmc2 and mmc3 interfaces switching characteristics high-speed jc64 mode (5) (6) (7) (continued) no. parameter opp100 opp50 unit min max min max mmc5 t d(clkl-dov) delay time, mmcx_clk rising clock edge to mmcx_cmd 3.6 16.8 4 37.2 ns transition t r(do) rising time, output mmcx_cmd 2263 2263 ps t f(do) falling time, output mmcx_cmd 2136 2136 ps mmc6 t d(clkl-dov) delay time, mmcx_clk rising clock edge to mmcx_daty 3.6 16.8 4 37.2 ns transition t r(do) rising time, output mmcx_dat[n:0] (4) 2263 2263 ps t f(do) falling time, output mmcx_dat[n:0] (4) 2136 2136 ps (1) related with the output clock maximum and minimum frequencies programmable in mmc module. (2) po = output clock period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) in mmx_dat[n:0], x is equal to 2 or 3 and n is equal to 7. (5) see section 4.3.4 , processor clocks . (6) in mmx_cmd, x is equal to 2 or 3. (7) in mmx_clk, x is equal to 2 or 3. figure 6-77. mmc2 and mmc3 interfaces high-speed jc64 transmiter mode (1) (2) (3) (1) in mmx_dat[n:0], x is equal to 2 or 3 and n is equal to 7. (2) in mmx_cmd, x is equal to 2 or 3. (3) in mmx_clk, x is equal to 2 or 3. figure 6-78. mmc2 and mmc3 interfaces high-speed jc64 receiver mode (1) (2) (3) (1) in mmx_dat[n:0], x is equal to 2 or 3 and n is equal to 7. (2) in mmx_cmd, x is equal to 2 or 3. (3) in mmx_clk, x is equal to 2 or 3. copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 263 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-104 mmcx_clk mmcx_cmd mmcx_dat[n:0] mmc5 mmc5 mmc6 mmc6 mmc1 mmc2 mmc2 swps038-105 mmcx_clk mmcx_cmd mmcx_dat[n:0] mmc4 mmc8 mmc3 mmc7 mmc1 mmc2 mmc2
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.6.9 test interfaces 6.6.9.1 embedded trace macro interface (etm) table 6-137 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-79 ). table 6-136. etm timing conditions transmit mode timing condition parameter value unit min max output condition c load output load capacitance (1) 10 pf (1) buffer strength configuration: lb0 = 1. table 6-137. etm switching characteristics transmit mode (4) no. parameter opp100 opp50 unit min max min max tpiu1 1 / t c(clk) frequency (3) , output clock etk_clk 166 166 mhz tpiu2 t w(clkh) pulse duration, output clock etk_clk high 0.5p (1) 0.5p (1) ns tpiu3 t w(clkl) pulse duration, output clock etk_clk low 0.5p (1) 0.5p (1) ns t dc(clk) duty cycle error, output clock etk_clk C 301 301 C 301 301 ps t j(clk) jitter standard deviation (2) , output clock etk_clk 65 65 ps t r(clk) rise time, output clock etk_clk 1.2 1.2 ns t f(clk) fall time, output clock etk_clk 1.2 1.2 ns tpiu4 t d(clk-ctl) delay time, output clock etk_clk low/high to output 0.839 0.839 ns control etk_ctl transition tpiu5 t d(clkh-d) delay time, output clock etk_clk low/high to output 0.839 0.839 ns data etk_d[15:0] transition t r(d/ctl) rise time, output data etk_d[15:0] and output control 1.2 1.2 ns etk_ctl t f(d/ctl) fall time, output data etk_d[15:0] and output control 1.2 1.2 ns etk_ctl (1) p = etk_clk period in ns (2) the jitter probability density can be approximated by a gaussian function. (3) related with the etm_clk maximum frequency. (4) see section 4.3.4 , processor clocks . figure 6-79. etm transmit mode 264 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 etk_clk etk_ctl etk_d[15:0] tpiu1 tpiu2 tpiu3 tpiu4 tpiu5 tpiu5 tpiu4 swps038-106
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 6.6.9.2 system debug trace interface (sdti) the system debug trace interface (sdti) module provides real-time software tracing functionality to the device. the trace interface has four trace data pins and a trace clock pin. this interface is a dual-edge interface: ? the data are available on rising and falling edge of sdti_clk. ? but can be also configured in single-edge mode where data are available on the falling edge of sdti_clk. serial interface operates in clock stop regime: serial clock is not free-running; when there is no trace data, there is no trace clock. 6.6.9.2.1 sdti dual-edge mode table 6-139 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-80 ). table 6-138. sdti timing conditions dual-edge mode timing condition parameter value unit output condition c load output load capacitance (1) 25 pf (1) buffer strength configuration: lb0 = 1. table 6-139. sdti switching characteristics dual-edge mode (2) no. parameter opp100 opp50 unit min max min max sd1 1 / t c(clk) frequency, output clock sdti_clk 34.5 34.5 mhz sd2 t w(clk) pulse duration, output clock sdti_clk high or low 0.5p (1) C 0.5p (1) + 0.5p (1) C 0.5p (1) + ns 1.2 1.2 1.2 1.2 sd3 t d(clk-txd) delay time, output clock sdti_clk multiplexing mode on 2.3 10.9 2.3 10.9 ns transition to output data etk pins sdti_txd[3:0] transition multiplexing mode on 2.3 13.9 2.3 13.9 jtag_emu pins (1) p = sdti_clk clock period in ns (2) see section 4.3.4 , processor clocks . figure 6-80. sdti dual-edge mode copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 265 submit documentation feedback product folder link(s): dm3730 dm3725 swps038-107 sdti_clk sdti_txd[3:0] header header ad[7:4] ad[3:0] da[15:12] da[11:8] da[7:4] da[3:0] sd1 sd2 sd3 sd3
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 6.6.9.2.2 sdti single-edge mode table 6-141 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-81 ). table 6-140. sdti timing conditions single-edge mode timing condition parameter value unit output condition c load output load capacitance (1) 25 pf (1) buffer strength configuration: lb0 = 1. table 6-141. sdti switching characteristics single-edge mode (2) no. parameter opp100 opp50 unit min max min max sd1 1 / t c(clk) frequency, output clock sdti_clk 34.5 34.5 mhz sd2 t w(clk) pulse duration, output clock sdti_clk high or low 0.5p (1) C 0.5p (1) + 0.5p (1) C 0.5p (1) + ns 1.2 1.2 1.2 1.2 sd3 t d(clk-txd) delay time, output clock sdti_clk multiplexing mode on 2.3 26.5 2.3 26.5 ns transition to output data etk pins sdti_txd[3:0] transition multiplexing mode on 2.3 33.2 2.3 33.2 jtag_emu pins (1) p = sdti_clk clock period in ns (2) see section 4.3.4 , processor clocks . figure 6-81. sdti single-edge mode 6.6.9.3 jtag interface (jtag) the jtag tap controller handles standard ieee jtag interfaces. the following section defines the timing requirements for several tools used to test the device as: ? free-running clock tool, like xds560 and xds510 tools ? adaptive clock tool, like realview ? ice tool and lauterbach tm tool 6.6.9.3.1 jtag free-running clock mode table 6-143 and table 6-144 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-82 ). table 6-142. jtag timing conditions free-running clock mode timing condition parameter value unit input conditions t r input signal rise time 5 ns t f input signal fall time 5 ns output condition c load output load capacitance 30 pf 266 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 swps038-108 sdti_clk sdti_txd[3:0] header header ad[7:4] ad[3:0] da[15:12] da[11:8] da[7:4] da[3:0] sd1 sd2 sd3 sd3
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 table 6-143. jtag timing requirements free-running clock mode (5) (6) no. parameter opp100 opp50 unit min max min max jt4 1 / t c(tck) frequency (1) , input clock jtag_tck 50 50 mhz jt5 t w(tckl) pulse duration, input clock jtag_tck low 0.5p (2) 0.5p (2) ns jt6 t w(tckh) pulse duration, input clock jtag_tck high 0.5p (2) 0.5p (2) ns t dc(tck) duty cycle error, input clock jtag_tck C 1250 1250 C 1667 1667 ps t j(tck) cycle jitter (3) , input clock jtag_tck C 1250 1250 C 1667 1667 ps jt7 t su(tdiv-rtckh) setup time, input data jtag_tdi valid before output 1.6 1.6 ns clock jtag_rtck high jt8 t h(tdiv-rtckh) hold time, input data jtag_tdi valid after output clock 0.7 1.0 ns jtag_rtck high jt9 t su(tmsv-rtckh) setup time, input mode select jtag_tms_tmsc valid 1.6 1.6 ns before output clock jtag_rtck high jt10 t h(tmsv-rtckh) hold time, input mode select jtag_tms_tmsc valid after 0.7 1.0 ns output clock jtag_rtck high jt12 t su(emuxv-rtckh) setup time, input emulation jtag_emux (4) valid before 14.4 19.6 ns output clock jtag_rtck high jt13 t h(emuxv-rtckh) hold time, input emulation jtag_emux (4) valid after 2.0 2.7 ns output clock jtag_rtck high (1) related with the input maximum frequency supported by the jtag module. (2) p = input clock jtag _tck period in ns (3) maximum cycle jitter supported by input clock jtag _tck. (4) in jtag_emux, x is equal to 0 or 1. (5) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (6) see section 4.3.4 , processor clocks . table 6-144. jtag switching characteristics free-running clock mode (5) no. parameter opp100 opp50 unit min max min max jt1 1 / t c(rtck) frequency (1) , output clock jtag_rtck 50 50 mhz jt2 t w(rtckl) pulse duration, output clock jtag_rtck low 0.5p (2) 0.5p (2) ns jt3 t w(rtckh) pulse duration, output clock jtag_rtck high 0.5p (2) 0.5p (2) ns t dc(rtck) duty cycle error, output clock jtag_rtck C 1250 1250 C 1667 1667 ps t j(rtck) jitter standard deviation (3) , output clock jtag_rtck 33.3 33.3 ps t r(rtck) rise time, output clock jtag_rtck 0 0 ns t f(rtck) fall time, output clock jtag_rtck 0 0 ns jt11 t d(rtckl-tdov) delay time, output clock jtag_rtck low to output data C 5.8 5.8 C 7.9 7.9 ns jtag_tdo valid t r(tdo) rise time, output data jtag_tdo 0 0 ns t f(tdo) fall time, output data jtag_tdo 0 0 ns jt14 t d(rtckh-emuxv) delay time, output clock jtag_rtck high to output 2.7 15.1 2.7 20.4 ns emulation ,jtag_emux (4) valid (1) related with the jtag_rtck maximum frequency. (2) p = output clock jtag _rtck period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) in jtag_emux, x is equal to 0 or 1. (5) see section 4.3.4 , processor clocks . copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 267 submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com (1) in jtag_emux, x is equal to 0 or 1. figure 6-82. jtag free-running clock mode 6.6.9.3.2 jtag adaptative clock mode table 6-146 and table 6-147 assume testing over the recommended operating conditions and electrical characteristic conditions below (see figure 6-83 ). table 6-145. jtag timing conditions adaptative clock mode timing condition parameter value unit input conditions t r input signal rise time 5 ns t f input signal fall time 5 ns output condition c load output load capacitance 30 pf table 6-146. jtag timing requirements adaptative clock mode (4) (5) no. parameter opp100 opp50 unit min max min max ja4 1 / t c(tck) frequency (1) , input clock jtag_tck 50 50 mhz ja5 t w(tckl) pulse duration, input clock jtag_tck low 0.5p (2) 0.5p (2) ns ja6 t w(tckh) pulse duration, input clock jtag_tck high 0.5p (2) 0.5p (2) ns t dc(lclk) duty cycle error, input clock jtag_tck C 2500 2500 C 2500 2500 ps t j(lclk) cycle jitter (3) , input clock jtag_tck C 1500 1500 C 1500 1500 ps ja7 t su(tdiv-tckh) setup time, input data jtag_tdi valid before input clock 13.8 13.8 ns jtag_tck high ja8 t h(tdiv-tckh) hold time, input data jtag_tdi valid after input clock 13.8 13.8 ns jtag_tck high ja9 t su(tmsv-tckh) setup time, input mode select jtag_tms_tmsc valid 13.8 13.8 ns before input clock jtag_tck high ja10 t h(tmsv-tckh) hold time, input mode select jtag_tms_tmsc valid after 13.8 13.8 ns input clock jtag_tck high 268 timing requirements and switching characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725 jtag_tck jtag_rtck jtag_tdi jtag_tms_tmsc jtag_emux(in) jtag_tdo jtag_emux(out) jt7 jt11 jt1 jt2 jt3 jt8 jt10 jt9 jt4 jt5 jt6 jt12 jt13 jt14 swps038-109
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 (1) related with the input maximum frequency supported by the jtag module (2) p = input clock jtag _tck period in ns (3) maximum cycle jitter supported by input clock jtag _tck. (4) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (5) see section 4.3.4 , processor clocks . table 6-147. jtag switching characteristics adaptative clock mode (4) no. parameter opp100 opp50 unit min max min max ja1 1 / t c(rtck) frequency (1) , output clock jtag_rtck 50 50 mhz ja2 t w(rtckl) pulse duration, output clock jtag_rtck low 0.5p (2) 0.5p (2) ns ja3 t w(rtckh) pulse duration, output clock jtag_rtck high 0.5p (2) 0.5p (2) ns t dc(rtck) duty cycle error, output clock jtag_rtck C 2500 2500 C 2500 2500 ps t j(rtck) jitter standard deviation (3) , output clock jtag_rtck 33.3 33.3 ps t r(rtck) rise time, output clock jtag_rtck 0 0 ns t f(rtck) fall time, output clock jtag_rtck 0 0 ns ja11 t d(rtckl-tdov) delay time, output clock jtag_rtck low to output data C 14.6 14.6 C 14.6 14.6 ns jtag_tdo valid (1) related to the jtag _rtck maximum frequency programmable. (2) p = output clock jtag _rtck period in ns (3) the jitter probability density can be approximated by a gaussian function. (4) see section 4.3.4 , processor clocks . figure 6-83. jtag adaptative clock mode copyright ? 2010 C 2011, texas instruments incorporated timing requirements and switching characteristics 269 submit documentation feedback product folder link(s): dm3730 dm3725 jtag_tck jtag_tdi jtag_tms jtag_rtck jtag_tdo ja1 ja2 ja3 ja4 ja5 ja6 ja7 ja8 ja10 ja9 ja11 swps038-110
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com 7 package characteristics 7.1 package thermal characteristics table 7-1 and table 7-2 provide the thermal resistance characteristics for the packages used on this device. note: this table provides simulation data and may not represent actual use-case values. table 7-1. thermal resistance characteristics 800mhz arm operation-4gb ddr + flash package power (w) (5) ja ( c/w) (2) jb ( c/w) (3) jc ( c/w) (4) board type cbp package 1.42 20.06 6.44 (6) 2s2p (1) cbc package 1.42 19.97 7.76 (6) 2s2p (1) cus package 1.05 24.75 11.06 7.06 2s2p (1) (1) the board types are defined by jedec (reference jedec standard jesd51-9, test board for array surface mount package thermal measurements). (2) ja (theta-ja) = thermal resistance junction-to-ambient, c/w (3) jb (theta-jb) = thermal resistance junction-to-board, c/w (4) jc (theta-jc) = thermal resistance junction-to-board, c/w (5) these power numbers are based on simulation results for dm37x. power numbers for cbp and cbc packages include the dm37x device and pop memory. cus package is dm37x only. (6) not applicable since these packages have memory package mounted on top. table 7-2. thermal resistance characteristics 1ghz arm operation-8gb ddr package power (w) (5) ja ( c/w) (2) jb ( c/w) (3) jc ( c/w) (4) board type cbp package 2.06 19.51 6.19 (6) 2s2p (1) cbc package 2.06 20.11 8.01 (6) 2s2p (1) cus package 1.4 24.75 11.06 7.06 2s2p (1) (1) the board types are defined by jedec (reference jedec standard jesd51-9, test board for array surface mount package thermal measurements). (2) ja (theta-ja) = thermal resistance junction-to-ambient, c/w (3) jb (theta-jb) = thermal resistance junction-to-board, c/w (4) jc (theta-jc) = thermal resistance junction-to-board, c/w (5) these power numbers are based on simulation results for dm37x. power numbers for cbp and cbc packages include the dm37x device and pop memory. cus package is dm37x only. (6) not applicable since these packages have memory package mounted on top. 7.2 device support 7.2.1 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all dm37x processors and support tools. each device has one of three prefixes: x, p, or null (no prefix). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmdx) through fully qualified production devices/tools (tmds). device development evolutionary flow: x experimental device that is not necessarily representative of the final devices electrical specifications and may not use production assembly flow. (tmx definition) p prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. (tmp definition) null production version of the silicon die that is fully qualified. (tms definition) 270 package characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 support tool development evolutionary flow: tmdx development support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development support product. tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: developmental product is intended for internal evaluation purposes. production devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. tis standard warranty applies. predictions show that prototype devices (x or p), have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. for additional description of the device nomenclature markings, see the processor silicon errata . figure 7-1. device nomenclature 7.2.2 documentation support 7.2.2.1 related documentation from texas instruments the following documents describe the dm3730/25 digital media processor. copies of these documents are available on the internet at www.ti.com . tip: enter the literature number in the search box provided at www.ti.com . the current documentation that describes the dm3730/25 digital media processor, related peripherals, and other technical collateral, is available in the product folder at: www.ti.com . sprugn4 . collection of documents providing detailed information on the sitara tm architecture including power, reset, and clock control, interrupts, memory map, and switch fabric interconnect. detailed information on the microprocessor unit (mpu) subsystem as well a functional description of the peripherals supported on dm3730/25devices is also included. 7.2.2.1.1 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. copyright ? 2010 C 2011, texas instruments incorporated package characteristics 271 submit documentation feedback product folder link(s): dm3730 dm3725 prefix x dm3730 ( ) x = experimental device p = prototype device blank = production device device package type cbp = 515-pin spbga cbc = 515-pin spbga cus = 423-pin spbga silicon revision cbp ( ) blank = commercial temperature a = extended temperature d = industrial temperature ( ) blank = tray r = tape and reel ( ) blank = 800 mhz cortex-a8 100 = 1ghz cortex-a8
dm3730 , dm3725 sprs685d C august 2010 C revised july 2011 www.ti.com ti embedded processors wiki texas instruments embedded processors wiki. established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 7.2.2.2 related documentation from other sources the following documents are related to the dm3730, dm3725 digital media processors. copies of these documents can be obtained directly from the internet or from your texas instruments representative. cortex-a8 technical reference manual . this is the technical reference manual for the cortex-a8 processor. a copy of this document can be obtained via the internet at http://infocenter.arm.com . please see the dm3730, dm3725 digital media processors silicon errata (literature number sprz319 ) to determine the revision of the cortex-a8 core used on your device. arm core cortex tm -a8 (at400/at401) errata notice. provides a list of advisories for the different revisions of the cortex-a8 processor. contact your ti representative for a copy of this document. please see the dm3730, dm3725 digital media processors silicon errata (literature number sprz319 ) to determine the revision of the cortex-a8 core used on your device. 272 package characteristics copyright ? 2010 C 2011, texas instruments incorporated submit documentation feedback product folder link(s): dm3730 dm3725
dm3730 , dm3725 www.ti.com sprs685d C august 2010 C revised july 2011 7.3 mechanical data copyright ? 2010 C 2011, texas instruments incorporated package characteristics 273 submit documentation feedback product folder link(s): dm3730 dm3725
package option addendum www.ti.com 12-feb-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples dm3725cbc active pop-fcbga cbc 515 119 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3725cbc dm3725cbc100 active pop-fcbga cbc 515 119 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3725cbc100 dm3725cbca active pop-fcbga cbc 515 119 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 105 dm3725cbca dm3725cbp active pop-fcbga cbp 515 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3725cbp dm3725cbp-as3 dm3725cbp100 active pop-fcbga cbp 515 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3725cbp100 dm3725cbp100-as3 dm3725cbpa active pop-fcbga cbp 515 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 105 dm3725cbpa dm3725cbpd100 active pop-fcbga cbp 515 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 dm3725cbpd100 dm3725cbpd100-as3 dm3725cbpdr100 active pop-fcbga cbp 515 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 dm3725cbpd100 dm3725cus active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3725cus dm3725cus100 active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3725cus100 dm3725cusa active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 105 dm3725cusa dm3725cusd100 active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 dm3725cusd100 dm3730cbc active pop-fcbga cbc 515 119 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3730cbc dm3730cbc100 active pop-fcbga cbc 515 119 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3730cbc100 dm3730cbca active pop-fcbga cbc 515 119 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 105 dm3730cbca dm3730cbcd100 active pop-fcbga cbc 515 119 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 dm3730cbcd100 dm3730cbp active pop-fcbga cbp 515 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3730cbp dm3730cbp-as3
package option addendum www.ti.com 12-feb-2017 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples dm3730cbp100 active pop-fcbga cbp 515 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3730cbp100 dm3730cbp100-as3 dm3730cbpa active pop-fcbga cbp 515 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 105 dm3730cbpa dm3730cbpd100 active pop-fcbga cbp 515 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 dm3730cbpd100 dm3730cbpd100-as3 dm3730cus active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3730cus dm3730cus100 active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3730cus100 dm3730cus100nep active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm3730cus100 dm3730cusa active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 105 dm3730cusa dm3730cusd100 active fcbga cus 423 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 dm3730cusd100 XDM3730CBP obsolete pop-fcbga cbp 515 tbd call ti call ti 0 to 90 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
package option addendum www.ti.com 12-feb-2017 addendum-page 3 (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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